From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Fri, 2 Oct 2015 10:32:14 +0200 Subject: [U-Boot] [PATCH] imx: mx6: correct enable_fec_anatop_clock In-Reply-To: <1441530947-29576-1-git-send-email-Peng.Fan@freescale.com> References: <1441530947-29576-1-git-send-email-Peng.Fan@freescale.com> Message-ID: <560E410E.5040008@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 06/09/2015 11:15, Peng Fan wrote: > We should follow 'read->set/clr bit->write' flow for enable_fec_anatop_clock, > otherwise we may overridden configuration before enable_fec_anatop_clock. > > Signed-off-by: Peng Fan > Cc: Stefano Babic > Cc: Cc: Fabio Estevam > --- > arch/arm/cpu/armv7/mx6/clock.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c > index ba6cc75..11efd12 100644 > --- a/arch/arm/cpu/armv7/mx6/clock.c > +++ b/arch/arm/cpu/armv7/mx6/clock.c > @@ -535,6 +535,8 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) > if (freq < ENET_25MHZ || freq > ENET_125MHZ) > return -EINVAL; > > + reg = readl(&anatop->pll_enet); > + > if (fec_id == 0) { > reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; > reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); > Applied to u-boot-imx, thanks! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================