From: Thomas Chou <thomas@wytron.com.tw>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] nios2: convert cache flush to use dm cpu data
Date: Sat, 10 Oct 2015 13:55:45 +0800 [thread overview]
Message-ID: <5618A861.5020409@wytron.com.tw> (raw)
In-Reply-To: <201510091642.02061.marex@denx.de>
Hi Marek,
On 10/09/2015 10:42 PM, Marek Vasut wrote:
>> In nios2, we don't skip the flushing when the inputs are not aligned
>> like that of arm926ejs. We always flush all cache lines in the range,
>> even if a single byte to flush is in request. So the inputs are rounded
>> to get the lower and upper cache lines range inside the cache flush
>> functions. The caller need not be aware of the detail.
>
> This is incorrect and all the places which produce these unaligned cache
> operations must be fixed.
I take a look into the cache flush operations in every arch of u-boot.
It turns out that the arm926ejs is the only platform that does such
cache line range check and skip. All other ARM and all other arch don't.
And the cache flush in Linux don't.
Best regards,
Thomas
next prev parent reply other threads:[~2015-10-10 5:55 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-06 8:20 [U-Boot] [PATCH] nios2: convert cache flush to use dm cpu data Thomas Chou
2015-10-08 21:39 ` Marek Vasut
2015-10-09 2:49 ` Ley Foon Tan
2015-10-09 8:00 ` Thomas Chou
2015-10-09 14:42 ` Marek Vasut
2015-10-10 5:55 ` Thomas Chou [this message]
2015-10-10 6:32 ` Thomas Chou
2015-10-10 18:18 ` Marek Vasut
2015-10-11 0:38 ` Thomas Chou
2015-10-11 12:15 ` Marek Vasut
2015-10-12 0:34 ` Thomas Chou
2015-10-12 10:30 ` Marek Vasut
2015-10-12 13:12 ` Thomas Chou
2015-10-12 13:29 ` Marek Vasut
2015-10-12 13:49 ` Wolfgang Denk
2015-10-13 1:04 ` Thomas Chou
2015-10-16 23:03 ` Marek Vasut
2015-10-17 3:22 ` Thomas Chou
2015-10-17 11:44 ` Marek Vasut
2015-10-10 18:12 ` Marek Vasut
2015-10-09 14:40 ` Marek Vasut
2015-10-09 12:58 ` [U-Boot] [PATCH v2] " Thomas Chou
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