From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Chou Date: Sat, 10 Oct 2015 13:55:45 +0800 Subject: [U-Boot] [PATCH] nios2: convert cache flush to use dm cpu data In-Reply-To: <201510091642.02061.marex@denx.de> References: <1444119600-31999-1-git-send-email-thomas@wytron.com.tw> <5617741A.6090704@wytron.com.tw> <201510091642.02061.marex@denx.de> Message-ID: <5618A861.5020409@wytron.com.tw> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Marek, On 10/09/2015 10:42 PM, Marek Vasut wrote: >> In nios2, we don't skip the flushing when the inputs are not aligned >> like that of arm926ejs. We always flush all cache lines in the range, >> even if a single byte to flush is in request. So the inputs are rounded >> to get the lower and upper cache lines range inside the cache flush >> functions. The caller need not be aware of the detail. > > This is incorrect and all the places which produce these unaligned cache > operations must be fixed. I take a look into the cache flush operations in every arch of u-boot. It turns out that the arm926ejs is the only platform that does such cache line range check and skip. All other ARM and all other arch don't. And the cache flush in Linux don't. Best regards, Thomas