From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Wed, 14 Oct 2015 12:19:41 -0700 Subject: [U-Boot] [Patch V4 12/17] armv8/fsl_lsch2: Add fsl_lsch2 SoC In-Reply-To: <1444823072-27287-13-git-send-email-Qianyu.Gong@freescale.com> References: <1444823072-27287-1-git-send-email-Qianyu.Gong@freescale.com> <1444823072-27287-13-git-send-email-Qianyu.Gong@freescale.com> Message-ID: <561EAACD.4000002@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 10/14/2015 04:44 AM, Gong Qianyu wrote: > From: Mingkai Hu > > Freescale LayerScape with Chassis Generation 2 is a set of SoCs with > ARMv8 cores and 2rd generation of Chassis. > > Signed-off-by: Li Yang > Signed-off-by: Hou Zhiqiang > Signed-off-by: Mingkai Hu > Signed-off-by: Gong Qianyu > --- > V2: > - remove FSL_LS102xA_DEVDISR3_PCIE from immap_lsch2.h > V3: > - Update MMU table initialization to match the latest code. > - Remove some dead code > - Rename #include to #include > V4: > - Add fsl_lsch2 to fsl-layerscape framework. > > arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 + > arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 | 10 + > arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 104 +++- > .../cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c | 116 +++++ > .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 136 +++++ > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 17 + > arch/arm/include/asm/arch-fsl-layerscape/config.h | 45 ++ > .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 91 ++++ > .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 555 +++++++++++++++++++++ > .../include/asm/arch-fsl-layerscape/ns_access.h | 158 ++++++ > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 6 + > arch/arm/include/asm/armv8/mmu.h | 1 + > include/common.h | 3 + > 13 files changed, 1241 insertions(+), 5 deletions(-) > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile > index 712917c..a94ccb5 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile > @@ -9,6 +9,10 @@ obj-y += lowlevel.o > obj-y += soc.o > ifneq ($(CONFIG_FSL_LSCH3),) > obj-y += fsl_lsch3_speed.o > +else > +ifneq ($(CONFIG_FSL_LSCH2),) > +obj-y += fsl_lsch2_speed.o > +endif Have you tried obj-$(CONFIG_FSL_LSCH2)? > endif > > obj-$(CONFIG_MP) += mp.o > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 > new file mode 100644 > index 0000000..a6ef830 > --- /dev/null > +++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 > @@ -0,0 +1,10 @@ > +# > +# Copyright 2015 Freescale Semiconductor > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +Freescale LayerScape with Chassis Generation 2 > + > +This architecture supports Freescale ARMv8 SoCs with Chassis generation 2, > +for example LS1043A. > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > index 8937461..03cc532 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > @@ -26,12 +26,13 @@ > > DECLARE_GLOBAL_DATA_PTR; > > -#ifdef CONFIG_FSL_LSCH3 > static struct cpu_type cpu_type_list[] = { > #ifdef CONFIG_LS2085A > CPU_TYPE_ENTRY(LS2085, LS2085, 8), > CPU_TYPE_ENTRY(LS2080, LS2080, 8), > CPU_TYPE_ENTRY(LS2045, LS2045, 4), > +#elif defined(CONFIG_LS1043A) > + CPU_TYPE_ENTRY(LS1043, LS1043, 4), > #endif > }; Is this #ifdef necessary? > > @@ -40,7 +41,11 @@ void cpu_name(char *name) > struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); > unsigned int i, svr, ver; > > +#ifdef CONFIG_FSL_LSCH3 > svr = in_le32(&gur->svr); > +#elif defined(CONFIG_FSL_LSCH2) > + svr = in_be32(&gur->svr); > +#endif > ver = SVR_SOC_VER(svr); > > for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) > @@ -55,7 +60,6 @@ void cpu_name(char *name) > if (i == ARRAY_SIZE(cpu_type_list)) > strcpy(name, "unknown"); > } > -#endif > > #ifndef CONFIG_SYS_DCACHE_OFF > > @@ -117,6 +121,28 @@ void cpu_name(char *name) > #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 > #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 > #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 > +#elif defined(CONFIG_FSL_LSCH2) > +#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 > +#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 > +#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000 > +#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000 > +#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000 > +#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000 > +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 > +#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000 > +#define CONFIG_SYS_FSL_IFC_BASE 0x60000000 > +#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000 > +#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 > +#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 > +#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000 > +#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 > +#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 > +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ > +#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 > +#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 > +#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 > +#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 > +#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ > #endif > > struct sys_mmu_table { > @@ -146,6 +172,17 @@ static const struct sys_mmu_table early_mmu_table[] = { > CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, > { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, > CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, > +#elif defined(CONFIG_FSL_LSCH2) > + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, > + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, > + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, > + CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, > + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, > + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, > + { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, > + CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, > + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, > + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, > { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, > CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, > #endif > @@ -194,6 +231,34 @@ static const struct sys_mmu_table final_mmu_table[] = { > CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, > { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, > CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, > +#elif defined(CONFIG_FSL_LSCH2) > + { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, > + CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, > + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, > + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, > + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, > + CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, > + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, > + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, > + { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, > + CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, > + { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, > + CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, > + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, > + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, > + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, > + { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, > + CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, > + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, > + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, > + { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, > + CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, > + { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, > + CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, > + { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, > + CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, > + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, > + CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE }, > #endif > }; > Maybe separating these tables is cleaner? > @@ -335,6 +400,8 @@ static inline void early_mmu_setup(void) > set_pgtable_table(level1_table0, > CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1, > level2_table1); > +#elif defined(CONFIG_FSL_LSCH2) > + set_pgtable_table(level1_table0, 1, level2_table1); > #endif > /* Find the table and fill in the block entries */ > for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) { > @@ -370,6 +437,9 @@ static inline void early_mmu_setup(void) > * > * For LSCH3: > * Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB. > + * For LSCH2: > + * Level 2 table 1 contains 512 entries for each 2MB from 1GB to 2GB. > + * Level 2 table 2 contains 512 entries for each 2MB from 20GB to 21GB. > */ > static inline void final_mmu_setup(void) > { > @@ -380,6 +450,9 @@ static inline void final_mmu_setup(void) > u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000); > #ifdef CONFIG_FSL_LSCH3 > u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); > +#elif defined(CONFIG_FSL_LSCH2) > + u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); > + u64 *level2_table2 = (u64 *)(gd->arch.tlb_addr + 0x5000); > #endif > struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; > > @@ -394,6 +467,11 @@ static inline void final_mmu_setup(void) > set_pgtable_table(level1_table0, > CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1, > level2_table1); > +#elif defined(CONFIG_FSL_LSCH2) > + set_pgtable_table(level1_table0, 1, level2_table1); > + set_pgtable_table(level1_table0, > + CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1, > + level2_table2); > #endif > > /* Find the table and fill in the block entries */ > @@ -458,6 +536,8 @@ static inline u32 initiator_type(u32 cluster, int init_id) > u32 type = 0; > #ifdef CONFIG_FSL_LSCH3 > type = in_le32(&gur->tp_ityp[idx]); > +#elif defined(CONFIG_FSL_LSCH2) > + type = in_be32(&gur->tp_ityp[idx]); > #endif Maybe consider to wrap up the in_be32 and in_le32? You have a lot of these. > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h > index 27d4582..aaa92c1 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h > @@ -50,6 +50,51 @@ > #define CONFIG_SYS_FSL_ERRATUM_A008514 > #define CONFIG_SYS_FSL_ERRATUM_A008585 > #define CONFIG_SYS_FSL_ERRATUM_A008751 > +#elif defined(CONFIG_LS1043A) > +#define CONFIG_MAX_CPUS 4 > +#define CONFIG_SYS_CACHELINE_SIZE 64 > +#define CONFIG_SYS_FMAN_V3 > +#define CONFIG_SYS_NUM_FMAN 1 > +#define CONFIG_SYS_NUM_FM1_DTSEC 7 > +#define CONFIG_SYS_NUM_FM1_10GEC 1 > +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 > +#define CONFIG_NUM_DDR_CONTROLLERS 1 > +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 > +#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 > +#define CONFIG_SYS_FSL_SEC_COMPAT 5 > +#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ > +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */ > +#define CONFIG_SYS_FSL_DDR_BE > +#ifdef CONFIG_SYS_FSL_DDR4 > +#define CONFIG_SYS_FSL_DDRC_GEN4 > +#else > +#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ > +#endif Move non-soc specific marcos out of #ifdef, please. York