[U-Boot] [PATCH] arm: ls102xa: enable snooping for CAAM transactions

["Horia Geantă" <horia.geanta@freescale.com>]

On 10/14/2015 11:54 PM, York Sun wrote:
> 
> 
> On 09/16/2015 03:22 AM, Horia Geant? wrote:
>> Enable snooping for CAAM read & write transactions by
>> programming the SCFG snoop configuration register:
>> SCFG_SNPCNFGCR[SECRDSNP]
>> SCFG_SNPCNFGCR[SECWRSNP]
>>
>> Signed-off-by: Horia Geant? <horia.geanta@freescale.com>
>> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
> 
> The Reviewed-by signature should be added by reviewer or maintainer.

It was added by Jason during an internal review.
Sorry for not adding him in Cc.

>> ---
>>  arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +
>>  board/freescale/ls1021aqds/ls1021aqds.c           | 2 ++
>>  board/freescale/ls1021atwr/ls1021atwr.c           | 2 ++
>>  3 files changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
>> index 60aa0d3b6f43..fbd06bafce31 100644
>> --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
>> +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
>> @@ -144,6 +144,7 @@ struct ccsr_gur {
>>  };
>>  
>>  #define SCFG_ETSECDMAMCR_LE_BD_FR	0x00000c00
>> +#define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
>>  #define SCFG_ETSECCMCR_GE2_CLK125	0x04000000
>>  #define SCFG_ETSECCMCR_GE0_CLK125	0x00000000
>>  #define SCFG_ETSECCMCR_GE1_CLK125	0x08000000
>> diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
>> index 655fc644fe90..e7c25a5012f0 100644
>> --- a/board/freescale/ls1021aqds/ls1021aqds.c
>> +++ b/board/freescale/ls1021aqds/ls1021aqds.c
>> @@ -281,6 +281,8 @@ int board_early_init_f(void)
>>  	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
>>  	unsigned int major;
>>  
>> +	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
>> +
>>  #ifdef CONFIG_TSEC_ENET
>>  	/* clear BD & FR bits for BE BD's and frame data */
>>  	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
>> diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
>> index 228dbf81bb25..e15999e42165 100644
>> --- a/board/freescale/ls1021atwr/ls1021atwr.c
>> +++ b/board/freescale/ls1021atwr/ls1021atwr.c
>> @@ -482,6 +482,8 @@ int board_early_init_f(void)
>>  	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
>>  	unsigned int major;
>>  
>> +	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
>> +
>>  #ifdef CONFIG_TSEC_ENET
>>  	/* clear BD & FR bits for BE BD's and frame data */
>>  	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
>>
> 
> Why wasn't the change put into arch_cpu_init?

Good point.
I'll make the update in v2.

Thanks,
Horia