[U-Boot] [PATCH] vf610twr: Fix typo in DRAM init

[U-Boot] [PATCH] vf610twr: Fix typo in DRAM init

[Anthony Felice]

This commit fixes a typo in vf610twr DRAM init that was causing a hang in
U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
(vf610: refactor DDRMC code).

Signed-off-by: Anthony Felice <tony.felice@timesys.com>
---
 board/freescale/vf610twr/vf610twr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
index a78e9e6..fa0075c 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -108,7 +108,7 @@ int dram_init(void)
 		.trcd_int          = 6,
 		.tras_lockout      = 0,
 		.tdal              = 12,
-		.bstlen            = 0,
+		.bstlen            = 3,
 		.tdll              = 512,
 		.trp_ab            = 6,
 		.tref              = 3120,
-- 
1.9.1

[U-Boot] [PATCH] vf610twr: Fix typo in DRAM init

[Otavio Salvador]

On Fri, Oct 9, 2015 at 5:38 PM, Anthony Felice <tony.felice@timesys.com> wrote:
> This commit fixes a typo in vf610twr DRAM init that was causing a hang in
> U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
> (vf610: refactor DDRMC code).
>
> Signed-off-by: Anthony Felice <tony.felice@timesys.com>

Seems fine for me. Stefano?

-- 
Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750

[U-Boot] [PATCH] vf610twr: Fix typo in DRAM init

[Fabio Estevam]

On Fri, Oct 9, 2015 at 5:38 PM, Anthony Felice <tony.felice@timesys.com> wrote:
> This commit fixes a typo in vf610twr DRAM init that was causing a hang in
> U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
> (vf610: refactor DDRMC code).
>
> Signed-off-by: Anthony Felice <tony.felice@timesys.com>

Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>

[U-Boot] [PATCH] vf610twr: Fix typo in DRAM init

[Fabio Estevam]

On Tue, Oct 13, 2015 at 12:28 PM, Fabio Estevam <festevam@gmail.com> wrote:
> On Fri, Oct 9, 2015 at 5:38 PM, Anthony Felice <tony.felice@timesys.com> wrote:
>> This commit fixes a typo in vf610twr DRAM init that was causing a hang in
>> U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
>> (vf610: refactor DDRMC code).
>>
>> Signed-off-by: Anthony Felice <tony.felice@timesys.com>
>
> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>

Also, adding the author of 3f353cecc ("vf610: refactor DDRMC code")
and the i.MX/Vybrid maintainer.

Thanks

[U-Boot] [PATCH] vf610twr: Fix typo in DRAM init

[Albert ARIBAUD]

Bonjour Fabio,

Le Tue, 13 Oct 2015 12:30:47 -0300, Fabio Estevam <festevam@gmail.com>
a ?crit :

> On Tue, Oct 13, 2015 at 12:28 PM, Fabio Estevam <festevam@gmail.com> wrote:
> > On Fri, Oct 9, 2015 at 5:38 PM, Anthony Felice <tony.felice@timesys.com> wrote:
> >> This commit fixes a typo in vf610twr DRAM init that was causing a hang in
> >> U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
> >> (vf610: refactor DDRMC code).
> >>
> >> Signed-off-by: Anthony Felice <tony.felice@timesys.com>
> >
> > Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
> 
> Also, adding the author of 3f353cecc ("vf610: refactor DDRMC code")
> and the i.MX/Vybrid maintainer.
> 
> Thanks

Thanks to Anthony for spotting and fixing this!

Cordialement,
Albert ARIBAUD
3ADEV

[U-Boot] [PATCH] vf610twr: Fix typo in DRAM init

[Fabio Estevam]

Hi Stefano,

On Tue, Oct 13, 2015 at 5:12 PM, Albert ARIBAUD <albert.aribaud@3adev.fr> wrote:

> Thanks to Anthony for spotting and fixing this!

This one fixes a regression. Please consider applying it to 2015.10.

Thanks

[U-Boot] [PATCH] vf610twr: Fix typo in DRAM init

[Stefan Agner]

Hi Anthony,

Tested on a Tower, works for me.

Can you also fix the Colibri VF board? It seems to suffer the same
issue, introduced by the same commit...

--
Stefan

On 2015-10-09 13:38, Anthony Felice wrote:
> This commit fixes a typo in vf610twr DRAM init that was causing a hang in
> U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
> (vf610: refactor DDRMC code).
> 
> Signed-off-by: Anthony Felice <tony.felice@timesys.com>
> ---
>  board/freescale/vf610twr/vf610twr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/board/freescale/vf610twr/vf610twr.c
> b/board/freescale/vf610twr/vf610twr.c
> index a78e9e6..fa0075c 100644
> --- a/board/freescale/vf610twr/vf610twr.c
> +++ b/board/freescale/vf610twr/vf610twr.c
> @@ -108,7 +108,7 @@ int dram_init(void)
>  		.trcd_int          = 6,
>  		.tras_lockout      = 0,
>  		.tdal              = 12,
> -		.bstlen            = 0,
> +		.bstlen            = 3,
>  		.tdll              = 512,
>  		.trp_ab            = 6,
>  		.tref              = 3120,

[U-Boot] [PATCH] vf610twr: Fix typo in DRAM init

[Tony Felice]

Hi Stefan,

Yes, I can submit the fix for the Colibri VF board as well - although I
don't have the Colibri board to boot test on. I will be out of the office
the next few days so I will submit next week.

Thanks,

Tony

On Tue, Oct 13, 2015 at 10:47 PM, Stefan Agner <stefan@agner.ch> wrote:

> Hi Anthony,
>
> Tested on a Tower, works for me.
>
> Can you also fix the Colibri VF board? It seems to suffer the same
> issue, introduced by the same commit...
>
> --
> Stefan
>
> On 2015-10-09 13:38, Anthony Felice wrote:
> > This commit fixes a typo in vf610twr DRAM init that was causing a hang in
> > U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
> > (vf610: refactor DDRMC code).
> >
> > Signed-off-by: Anthony Felice <tony.felice@timesys.com>
> > ---
> >  board/freescale/vf610twr/vf610twr.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/board/freescale/vf610twr/vf610twr.c
> > b/board/freescale/vf610twr/vf610twr.c
> > index a78e9e6..fa0075c 100644
> > --- a/board/freescale/vf610twr/vf610twr.c
> > +++ b/board/freescale/vf610twr/vf610twr.c
> > @@ -108,7 +108,7 @@ int dram_init(void)
> >               .trcd_int          = 6,
> >               .tras_lockout      = 0,
> >               .tdal              = 12,
> > -             .bstlen            = 0,
> > +             .bstlen            = 3,
> >               .tdll              = 512,
> >               .trp_ab            = 6,
> >               .tref              = 3120,
>
>


-- 
Tony Felice
Vybrid Technical Lead
Timesys Corporation

[U-Boot] [PATCH] vf610twr: Fix typo in DRAM init

[Stefan Agner]

Hi Tony,

I then realized that we are close to the release and submitted an
individual patch right away. So you don't need to create a patch. Thanks
for uncovering the bug and the offer. 

Patch, see:
https://patchwork.ozlabs.org/patch/529985/

--
Stefan

On 2015-10-14 16:29, Tony Felice wrote: 

> Hi Stefan,
> 
> Yes, I can submit the fix for the Colibri VF board as well - although I don't have the Colibri board to boot test on. I will be out of the office the next few days so I will submit next week.
> 
> Thanks,
> 
> Tony 
> 
> On Tue, Oct 13, 2015 at 10:47 PM, Stefan Agner <stefan@agner.ch> wrote:
> 
>> Hi Anthony,
>> 
>> Tested on a Tower, works for me.
>> 
>> Can you also fix the Colibri VF board? It seems to suffer the same
>> issue, introduced by the same commit...
>> 
>> --
>> Stefan
>> 
>> On 2015-10-09 13:38, Anthony Felice wrote:
>>> This commit fixes a typo in vf610twr DRAM init that was causing a hang in
>>> U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
>>> (vf610: refactor DDRMC code).
>>> 
>>> Signed-off-by: Anthony Felice <tony.felice@timesys.com>
>>> ---
>>> board/freescale/vf610twr/vf610twr.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>> 
>>> diff --git a/board/freescale/vf610twr/vf610twr.c
>>> b/board/freescale/vf610twr/vf610twr.c
>>> index a78e9e6..fa0075c 100644
>>> --- a/board/freescale/vf610twr/vf610twr.c
>>> +++ b/board/freescale/vf610twr/vf610twr.c
>>> @@ -108,7 +108,7 @@ int dram_init(void)
>>> .trcd_int = 6,
>>> .tras_lockout = 0,
>>> .tdal = 12,
>>> - .bstlen = 0,
>>> + .bstlen = 3,
>>> .tdll = 512,
>>> .trp_ab = 6,
>>> .tref = 3120,
> 
> -- 
> 
> Tony Felice
> Vybrid Technical Lead Timesys Corporation

[U-Boot] [PATCH] vf610twr: Fix typo in DRAM init

[Stefan Agner]

Hi Stefano,

This patch did not make it into the git tree, however my patch which
followed that one (and which fixed the same issue on colibri_vf only),
did make it...

Sorry, my comment below was somewhat confusing. I descided afterwards to
just send a seperate one for colibri_vf.

Could you also merge this one into 2015.10?

--
Stefan

On 2015-10-14 16:54, Stefan Agner wrote:
> Hi Tony,
> 
> I then realized that we are close to the release and submitted an
> individual patch right away. So you don't need to create a patch. Thanks
> for uncovering the bug and the offer. 
> 
> Patch, see:
> https://patchwork.ozlabs.org/patch/529985/
> 
> --
> Stefan
> 
> On 2015-10-14 16:29, Tony Felice wrote: 
> 
>> Hi Stefan,
>>
>> Yes, I can submit the fix for the Colibri VF board as well - although I don't have the Colibri board to boot test on. I will be out of the office the next few days so I will submit next week.
>>
>> Thanks,
>>
>> Tony
>>
>> On Tue, Oct 13, 2015 at 10:47 PM, Stefan Agner <stefan@agner.ch> wrote:
>>
>>> Hi Anthony,
>>>
>>> Tested on a Tower, works for me.
>>>
>>> Can you also fix the Colibri VF board? It seems to suffer the same
>>> issue, introduced by the same commit...
>>>
>>> --
>>> Stefan
>>>
>>> On 2015-10-09 13:38, Anthony Felice wrote:
>>>> This commit fixes a typo in vf610twr DRAM init that was causing a hang in
>>>> U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
>>>> (vf610: refactor DDRMC code).
>>>>
>>>> Signed-off-by: Anthony Felice <tony.felice@timesys.com>
>>>> ---
>>>> board/freescale/vf610twr/vf610twr.c | 2 +-
>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/board/freescale/vf610twr/vf610twr.c
>>>> b/board/freescale/vf610twr/vf610twr.c
>>>> index a78e9e6..fa0075c 100644
>>>> --- a/board/freescale/vf610twr/vf610twr.c
>>>> +++ b/board/freescale/vf610twr/vf610twr.c
>>>> @@ -108,7 +108,7 @@ int dram_init(void)
>>>> .trcd_int = 6,
>>>> .tras_lockout = 0,
>>>> .tdal = 12,
>>>> - .bstlen = 0,
>>>> + .bstlen = 3,
>>>> .tdll = 512,
>>>> .trp_ab = 6,
>>>> .tref = 3120,
>>
>> --
>>
>> Tony Felice
>> Vybrid Technical Lead Timesys Corporation
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
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[U-Boot] [PATCH] vf610twr: Fix typo in DRAM init

[Stefano Babic]

Hi Stefan,

On 16/10/2015 08:32, Stefan Agner wrote:
> Hi Stefano,
> 
> This patch did not make it into the git tree, however my patch which
> followed that one (and which fixed the same issue on colibri_vf only),
> did make it...
> 
> Sorry, my comment below was somewhat confusing. I descided afterwards to
> just send a seperate one for colibri_vf.
> 
> Could you also merge this one into 2015.10?

Yes, I was quite confused. I have seen more patches (from you, Anthony
and Fabio) fixing the same issue, and I missed that only two of them
overlap. Fabio's patch (already merged) fixes the same issue on
colibri_vf, vf610twr is still broken.

I merge it and I ask Tom how to proceed. Maybe he prefer to pick it up
himself.

Best regards,
Stefano

-- 
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[U-Boot] vf610twr: Fix typo in DRAM init

[Tom Rini]

On Fri, Oct 09, 2015 at 04:38:39PM -0400, Anthony Felice wrote:

> This commit fixes a typo in vf610twr DRAM init that was causing a hang in
> U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
> (vf610: refactor DDRMC code).
> 
> Signed-off-by: Anthony Felice <tony.felice@timesys.com>
> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>

Applied to u-boot/master, thanks!

-- 
Tom
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