From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Chou Date: Sat, 17 Oct 2015 10:59:06 +0800 Subject: [U-Boot] [PATCH v4] nios2: convert dma_alloc_coherent to use malloc_cache_aligned In-Reply-To: <201510170056.47834.marex@denx.de> References: <1444013823-11909-1-git-send-email-thomas@wytron.com.tw> <201510121546.14072.marex@denx.de> <561C4DB1.9090502@wytron.com.tw> <201510170056.47834.marex@denx.de> Message-ID: <5621B97A.5070107@wytron.com.tw> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 10/17/2015 06:56 AM, Marek Vasut wrote: >> But nios2 cpu with 4 bytes >> dcache line size does not support this instruction. So we don't >> implement the invalidate_dcache_range/all() in u-boot yet. > > Where did you find this information ? Please find it on the foot note of table 7, page 8 of "Nios II Core Implementation Detail" manual, The 4-byte line data cache implementation substitutes the flushd instruction for the flushda instruction and triggers an unimplemented instruction exception for the initda instruction. The 16-byte and 32-byte line data cache implementations fully support the flushda and initda instructions. Best regards, Thomas