[U-Boot] [PATCH V2 06/14] imx: mx6: crm_reg: add LCDIF related macros

[Stefano Babic <sbabic@denx.de>]

On 20/10/2015 13:39, Peng Fan wrote:
> Add i.MX6UL/SX LCDIF related macros. Discard uneccessary
> '#ifdef xxx'.
> 
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> 
> V2:
>  none
> 
>  arch/arm/include/asm/arch-mx6/crm_regs.h | 34 ++++++++++++++++++++++++++++----
>  1 file changed, 30 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
> index 10306cd..13e0a3d 100644
> --- a/arch/arm/include/asm/arch-mx6/crm_regs.h
> +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
> @@ -174,6 +174,9 @@ struct mxc_ccm_reg {
>  #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET		29
>  #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK		(0x7 << 26)
>  #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET		26
> +/* LCDIF on i.MX6SX/UL */
> +#define MXC_CCM_CBCMR_LCDIF1_PODF_MASK                  (0x7 << 23)
> +#define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET                23
>  #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK		(0x7 << 23)
>  #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET		23
>  #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK		(0x3 << 21)
> @@ -210,7 +213,10 @@ struct mxc_ccm_reg {
>  #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET			27
>  #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK		(0x7 << 23)
>  #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET	23
> -/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
> +/* LCFIF2_PODF on i.MX6SX */
> +#define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK			(0x7 << 20)
> +#define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET               20
> +/* ACLK_EMI on i.MX6DQ/SDL/DQP */
>  #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK		(0x7 << 20)
>  #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET		20
>  /* CSCMR1_GPMI/BCH exist on i.MX6UL */
> @@ -400,6 +406,20 @@ struct mxc_ccm_reg {
>  #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET		19
>  /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
>  #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK		(0x1 << 18)
> +/* LCDIF1 on i.MX6SX/UL */
> +#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK             (0x7 << 15)
> +#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET           15
> +#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK              (0x7 << 12)
> +#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET            12
> +#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK              (0x7 << 9)
> +#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET            9
> +/* LCDIF2 on i.MX6SX */
> +#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK             (0x7 << 6)
> +#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET           6
> +#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK              (0x7 << 3)
> +#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET            3
> +#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK              (0x7 << 0)
> +#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET             0
>  
>  /* All IPU2_DI1 are LCDIF1 on MX6SX */
>  #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
> @@ -622,17 +642,16 @@ struct mxc_ccm_reg {
>  #define MXC_CCM_CCGR2_IPMUX3_MASK			(3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
>  #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET	22
>  #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
> -#ifdef CONFIG_MX6SX
> +/* i.MX6SX/UL LCD and PXP */
>  #define MXC_CCM_CCGR2_LCD_OFFSET			28
>  #define MXC_CCM_CCGR2_LCD_MASK				(3 << MXC_CCM_CCGR2_LCD_OFFSET)
>  #define MXC_CCM_CCGR2_PXP_OFFSET			30
>  #define MXC_CCM_CCGR2_PXP_MASK				(3 << MXC_CCM_CCGR2_PXP_OFFSET)
> -#else
> +
>  #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET	24
>  #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
>  #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET	26
>  #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
> -#endif
>  
>  /* Exist on i.MX6SX */
>  #define MXC_CCM_CCGR3_M4_OFFSET					2
> @@ -685,6 +704,13 @@ struct mxc_ccm_reg {
>  #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK			(3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
>  #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET		26
>  #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK			(3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
> +
> +#define MXC_CCM_CCGR3_DISP_AXI_OFFSET                           6
> +#define MXC_CCM_CCGR3_DISP_AXI_MASK                             (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET)
> +#define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET                         8
> +#define MXC_CCM_CCGR3_LCDIF2_PIX_MASK                           (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET)
> +#define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET                         10
> +#define MXC_CCM_CCGR3_LCDIF1_PIX_MASK                           (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET)
>  /* AXI on i.MX6UL */
>  #define MXC_CCM_CCGR3_AXI_CLK_OFFSET				28
>  #define MXC_CCM_CCGR3_AXI_CLK_MASK				(3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
> 

Reviewed-by: Stefano Babic <sbabic@denx.de>

Best regards,
Stefano Babic

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