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[82.149.19.102]) by smtp.gmail.com with ESMTPSA id 23-20020a170906329700b00770812e2394sm2315039ejw.160.2022.12.11.10.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Dec 2022 10:33:46 -0800 (PST) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: andre.przywara@arm.com, jagan@amarulasolutions.com Cc: u-boot@lists.denx.de Subject: Re: [PATCH 8/8] sunxi: Parameterize H616 DRAM code some more Date: Sun, 11 Dec 2022 19:33:45 +0100 Message-ID: <5626428.DvuYhMxLoT@jernej-laptop> In-Reply-To: <20221211163213.98540-9-jernej.skrabec@gmail.com> References: <20221211163213.98540-1-jernej.skrabec@gmail.com> <20221211163213.98540-9-jernej.skrabec@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Dne nedelja, 11. december 2022 ob 17:32:13 CET je Jernej Skrabec napisal(a): > Part of the code, previously known as "unknown feature" also doesn't > have constant values. They are derived from TPR0 parameter in vendor > DRAM code. Introduce that parameter here too, to ease adding new boards. > > Signed-off-by: Jernej Skrabec > --- > .../include/asm/arch-sunxi/dram_sun50i_h616.h | 1 + > arch/arm/mach-sunxi/Kconfig | 6 ++++ > arch/arm/mach-sunxi/dram_sun50i_h616.c | 35 +++++++++++++++---- > 3 files changed, 35 insertions(+), 7 deletions(-) > diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c > b/arch/arm/mach-sunxi/dram_sun50i_h616.c index df06cea42464..6d8f8d371bfe > 100644 > --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c > +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c > @@ -808,15 +808,35 @@ static bool mctl_phy_init(struct dram_para *para) > writel(phy_init[i], &ptr[i]); > > if (para->tpr10 & TPR10_UNKNOWN_FEAT0) { > + if (para->tpr0 & BIT(30)) > + val = (para->tpr0 >> 7) & 0x3e; > + else > + val = (para->tpr10 >> 3) & 0x1e; > + > ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x780); > for (i = 0; i < 32; i++) > - writel(0x16, &ptr[i]); > - writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x78c); > - writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7a4); > - writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7b8); > - writel(0x8, SUNXI_DRAM_PHY0_BASE + 0x7d4); > - writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7dc); > - writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7e0); > + writel(val, &ptr[i]); > + > + val = (para->tpr10 << 1) & 0x1e; > + writel(val, SUNXI_DRAM_PHY0_BASE + 0x7dc); > + writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e0); > + > + /* following configuration is DDR3 specific */ > + val = (para->tpr10 >> 7) & 0x1e; > + writel(val, SUNXI_DRAM_PHY0_BASE + 0x7d4); > + /* > + * TODO: Offsets 0x79c, 0x794 and 0x7e4 may need > + * to be set here. However, this doesn't seem to > + * be needed by any board seen in the wild for now. > + * It's not implemented because it would unnecessarily > + * introduce PARA2 and TPR2 options. > + */ I just noticed that PARA2 check actually checks rank. I think it's important to implement it (register 0x79c) and uses only TPR10 value, which is already present. Best regards, Jernej > + if (para->tpr0 & BIT(31)) { > + val = (para->tpr0 << 1) & 0x3e; > + writel(val, SUNXI_DRAM_PHY0_BASE + 0x78c); > + writel(val, SUNXI_DRAM_PHY0_BASE + 0x7a4); > + writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8); > + } > } > > writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc);