[U-Boot] [PATCH v0 3/5] arm: mvebu: Fix SAR1_CPU_CORE_MASK

[Stefan Roese <sr@denx.de>]

Hi Dirk,

On 28.10.2015 16:44, dirk.eibach at gdsys.cc wrote:
> From: Dirk Eibach <dirk.eibach@gdsys.cc>
>
> SAR1_CPU_CORE_MASK was wrong, probably copy/paste
> from another architecture.
>
> Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
> ---
>
>   drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h | 7 ++-----
>   1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h b/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h
> index 7500a72..06d0ab1 100644
> --- a/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h
> +++ b/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h
> @@ -23,8 +23,8 @@
>
>   #define CPU_CONFIGURATION_REG(id)	(0x21800 + (id * 0x100))
>   #define CPU_MRVL_ID_OFFSET		0x10
> -#define SAR1_CPU_CORE_MASK		0x00000018
> -#define SAR1_CPU_CORE_OFFSET		3
> +#define SAR1_CPU_CORE_MASK		0x38000000
> +#define SAR1_CPU_CORE_OFFSET		27
>
>   #define NEW_FABRIC_TWSI_ADDR		0x4e
>   #ifdef DB_784MP_GP
> @@ -461,7 +461,4 @@
>   #define CLK_CPU_2200			13
>   #define CLK_CPU_2400			14
>
> -#define SAR1_CPU_CORE_MASK		0x00000018
> -#define SAR1_CPU_CORE_OFFSET		3
> -
>   #endif /* _DDR3_HWS_HW_TRAINING_DEF_H */

Thanks for spotting. Seems to be correct from the datasheet. How did
you find this problem? What exactly did happen on your board?

Reviewed-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan