From mboxrd@z Thu Jan 1 00:00:00 1970 From: Michal Simek Date: Wed, 4 Nov 2015 14:40:41 +0100 Subject: [U-Boot] [PATCH 8/8] net: zynq: Fix MDC setting for zynq In-Reply-To: References: <83dfb7b24aef979299a99bf6112c93c497be0b0d.1445959075.git.michal.simek@xilinx.com> Message-ID: <563A0AD9.6090004@xilinx.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 11/02/2015 10:39 PM, Joe Hershberger wrote: > On Tue, Oct 27, 2015 at 10:17 AM, Michal Simek wrote: >> Based on spec: >> "MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and >> write operations)" >> Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47 > > Isn't it dependent on which board and what the clock setup is? Should > this be specified by the board? I am not aware about it. It is related to internal chip clock. I expect that 111MHz is software default value is is used by most of the chip. The clock range based on mainline Linux driver is 80MHz - 120MHz that's why I expect all non standard configuration will fit to it. For lower values as we used till now none reported any functional issue too. > >> which is above of 2.5MHz. >> Using 48 divider will give us correct setting according spec >> (111/48=2.31). >> >> Signed-off-by: Michal Simek > > Acked-by: Joe Hershberger > Thanks, Michal