From mboxrd@z Thu Jan  1 00:00:00 1970
From: York Sun <yorksun@freescale.com>
Date: Wed, 4 Nov 2015 10:46:13 -0800
Subject: [U-Boot] [PATCH 4/5] armv7/fsl-ls102xa: Workaround for DDR
	erratum A008514
In-Reply-To: <1445422497-29230-4-git-send-email-yao.yuan@freescale.com>
References: <1445422497-29230-1-git-send-email-yao.yuan@freescale.com>
 <1445422497-29230-4-git-send-email-yao.yuan@freescale.com>
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On 10/21/2015 03:14 AM, Yuan Yao wrote:
> Affects: DDR
> Description: Memory controller performance is not optimal with default
> internal target queue register values.
> Impact: Memory controller performance is not optimal.
> Workaround: Write a value of 63b2_0002h to address: 157_020Ch.
> 
>
Please rewrite the commit message to explain why and what this patch does, not
copy-n-paste from erratum document.

York