[U-Boot] [PATCH 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514

Yuan Yao
2015-10-21T10:14:56Z

Affects: DDR
Description: Memory controller performance is not optimal with default
internal target queue register values.
Impact: Memory controller performance is not optimal.
Workaround: Write a value of 63b2_0002h to address: 157_020Ch.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
---
arch/arm/cpu/armv7/ls102xa/soc.c | 10 ++++++++++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +-
2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 97ba6d5..b15cd60 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -76,5 +76,15 @@ int arch_soc_init(void)
SCFG_SNPCNFGCR_DBG_RD_WR |
SCFG_SNPCNFGCR_EDMA_SNP);

+ /*
+ * Memory controller require a register write before being enabled.
+ * Affects: DDR
+ * Register: EDDRTQCFG
+ * Description: Memory controller performance is not optimal with
+ * default internal target queue register values.
+ * Workaround: Write a value of 63b2_0002h to address: 157_020Ch.
+ */
+ out_be32(&scfg->eddrtqcfg, 0x63b20002);
+
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 950347a..adb0e05 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -227,7 +227,7 @@ struct ccsr_scfg {
u32 scfgrevcr;
u32 coresrencr;
u32 pex2pmrdsr;
- u32 ddrc1cr;
+ u32 eddrtqcfg;
u32 ddrc2cr;
u32 ddrc3cr;
u32 ddrc4cr;
--
2.1.0.27.g96db324