[U-Boot] [PATCH v2] dm: implement a cfi flash uclass

Bin Meng
2015-10-11T07:54:40Z

+Simon,

Hi Thomas,

On Sun, Oct 11, 2015 at 3:30 PM, Thomas Chou <thomas@wytron.com.tw> wrote:
> Implement a cfi flash uclass to work with drivers/mtd/cfi-flash.c.
> The flash base address is extracted from device tree, and passed
> to cfi_flash_bank_addr().
>
> The current code supports only one bank. It should be extended to
> support multiple banks by decoding multiple "reg" tuples, eg,
> reg = <0 0x00000000 0x02000000
> 0 0x02000000 0x02000000>;
>
> Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
> ---
> v2
> add dts binding.
> add more help to Kconfig.
> move struct platdata to top of file as Simon suggested.
>
> common/board_r.c | 3 +
> configs/nios2-generic_defconfig | 1 +
> doc/device-tree-bindings/mtd/mtd-physmap.txt | 88 ++++++++++++++++++++++++++++
> drivers/mtd/Kconfig | 16 +++++
> drivers/mtd/Makefile | 1 +
> drivers/mtd/cfi-flash-uclass.c | 70 ++++++++++++++++++++++
> drivers/mtd/cfi_flash.c | 18 ++++++
> include/cfi-flash.h | 27 +++++++++
> include/dm/uclass-id.h | 1 +
> 9 files changed, 225 insertions(+)
> create mode 100644 doc/device-tree-bindings/mtd/mtd-physmap.txt
> create mode 100644 drivers/mtd/cfi-flash-uclass.c
> create mode 100644 include/cfi-flash.h
>
> diff --git a/common/board_r.c b/common/board_r.c
> index a4facf8..fceaea6 100644
> --- a/common/board_r.c
> +++ b/common/board_r.c
> @@ -38,6 +38,7 @@
> #include <miiphy.h>
> #endif
> #include <mmc.h>
> +#include <mtd/cfi_flash.h>
> #include <nand.h>
> #include <onenand_uboot.h>
> #include <scsi.h>
> @@ -348,6 +349,8 @@ static int initr_flash(void)
> /* update start of FLASH memory */
> #ifdef CONFIG_SYS_FLASH_BASE
> bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
> +#else
> + bd->bi_flashstart = cfi_flash_bank_addr(0);
> #endif
> /* size of FLASH memory (final value) */
> bd->bi_flashsize = flash_size;
> diff --git a/configs/nios2-generic_defconfig b/configs/nios2-generic_defconfig
> index 3d404b2..7b504ba 100644
> --- a/configs/nios2-generic_defconfig
> +++ b/configs/nios2-generic_defconfig
> @@ -18,6 +18,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
> CONFIG_ALTERA_PIO=y
> CONFIG_MISC=y
> CONFIG_ALTERA_SYSID=y
> +CONFIG_CFI_FLASH=y
> CONFIG_ALTERA_JTAG_UART=y
> CONFIG_ALTERA_JTAG_UART_BYPASS=y
> CONFIG_TIMER=y
> diff --git a/doc/device-tree-bindings/mtd/mtd-physmap.txt b/doc/device-tree-bindings/mtd/mtd-physmap.txt
> new file mode 100644
> index 0000000..a04d6e8
> --- /dev/null
> +++ b/doc/device-tree-bindings/mtd/mtd-physmap.txt
> @@ -0,0 +1,88 @@
> +CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
> +
> +Flash chips (Memory Technology Devices) are often used for solid state
> +file systems on embedded devices.
> +
> + - compatible : should contain the specific model of mtd chip(s)
> + used, if known, followed by either "cfi-flash", "jedec-flash",
> + "mtd-ram" or "mtd-rom".
> + - reg : Address range(s) of the mtd chip(s)
> + It's possible to (optionally) define multiple "reg" tuples so that
> + non-identical chips can be described in one node.
> + - bank-width : Width (in bytes) of the bank. Equal to the
> + device width times the number of interleaved chips.
> + - device-width : (optional) Width of a single mtd chip. If
> + omitted, assumed to be equal to 'bank-width'.
> + - #address-cells, #size-cells : Must be present if the device has
> + sub-nodes representing partitions (see below). In this case
> + both #address-cells and #size-cells must be equal to 1.
> + - no-unaligned-direct-access: boolean to disable the default direct
> + mapping of the flash.
> + On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause
> + problems with JFFS2 usage, as the local bus (LPB) doesn't support
> + unaligned accesses as implemented in the JFFS2 code via memcpy().
> + By defining "no-unaligned-direct-access", the flash will not be
> + exposed directly to the MTD users (e.g. JFFS2) any more.
> + - linux,mtd-name: allow to specify the mtd name for retro capability with
> + physmap-flash drivers as boot loader pass the mtd partition via the old
> + device name physmap-flash.
> + - use-advanced-sector-protection: boolean to enable support for the
> + advanced sector protection (Spansion: PPB - Persistent Protection
> + Bits) locking.
> +
> +For JEDEC compatible devices, the following additional properties
> +are defined:
> +
> + - vendor-id : Contains the flash chip's vendor id (1 byte).
> + - device-id : Contains the flash chip's device id (1 byte).
> +
> +For ROM compatible devices (and ROM fallback from cfi-flash), the following
> +additional (optional) property is defined:
> +
> + - erase-size : The chip's physical erase block size in bytes.
> +
> +The device tree may optionally contain sub-nodes describing partitions of the
> +address space. See partition.txt for more detail.
> +
> +Example:
> +
> + flash at ff000000 {
> + compatible = "amd,am29lv128ml", "cfi-flash";
> + reg = <ff000000 01000000>;
> + bank-width = <4>;
> + device-width = <1>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + fs at 0 {
> + label = "fs";
> + reg = <0 f80000>;
> + };
> + firmware at f80000 {
> + label ="firmware";
> + reg = <f80000 80000>;
> + read-only;
> + };
> + };
> +
> +Here an example with multiple "reg" tuples:
> +
> + flash at f0000000,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "intel,PC48F4400P0VB", "cfi-flash";

PC48F4400P0VB should be lower cases

> + reg = <0 0x00000000 0x02000000
> + 0 0x02000000 0x02000000>;
> + bank-width = <2>;
> + partition at 0 {
> + label = "test-part1";
> + reg = <0 0x04000000>;
> + };
> + };
> +
> +An example using SRAM:
> +
> + sram at 2,0 {
> + compatible = "samsung,k6f1616u6a", "mtd-ram";
> + reg = <2 0 0x00200000>;
> + bank-width = <2>;
> + };

By looking at the implementation, is it really necessary to add a new
uclass for cfi-flash, given we only need get the flash base address?
There are no cfi-flash specific ops defined.
Why not just read its base address from device tree?

[snip]

Regards,
Bin