[U-Boot] [PATCH] arm: socfpga: Fix cache configuration

Marek Vasut
2015-12-03T00:10:29Z

On Thursday, November 12, 2015 at 03:33:42 AM, Chin Liang See wrote:
> On Thu, 2015-11-12 at 01:53 +0100, Marek Vasut wrote:
> > On Thursday, November 12, 2015 at 01:49:09 AM, Chin Liang See wrote:
> > > Hi Marek,
> > >
> > > On Mon, 2015-11-09 at 17:02 +0100, Marek Vasut wrote:
> > > > On Monday, November 09, 2015 at 04:46:54 PM, Stefan Roese wrote:
> > > > > Hi Marek,
> > > >
> > > > Hi!
> > > >
> > > > > On 09.11.2015 14:49, Marek Vasut wrote:
> > > > >
> > > > > <snip>
> > > > >
> > > > > >>>> --- a/include/configs/socfpga_common.h
> > > > > >>>> +++ b/include/configs/socfpga_common.h
> > > > > >>>> @@ -73,7 +73,6 @@
> > > > > >>>>
> > > > > >>>> /*
> > > > > >>>>
> > > > > >>>> * Cache
> > > > > >>>> */
> > > > > >>>>
> > > > > >>>> -#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
> > > > > >>>>
> > > > > >>>> #define CONFIG_SYS_CACHELINE_SIZE 32
> > > > > >>>> #define CONFIG_SYS_L2_PL310
> > > > > >>>> #define CONFIG_SYS_PL310_BASE
SOCFPGA_MPUL2_ADDRESS
> > > > > >>>
> > > > > >>> I hate to say it, but I am running into issues with this patch
> > > > > >>> :-(
> > > > > >>
> > > > > >> I'm sorry to hear this.
> > > > > >>
> > > > > >>> I use a standard USB stick here and with this patch, I am
> > > > > >>> getting the following failure (with enabled and disabled
> > > > > >>> cache):
> > > > > >>>
> > > > > >>> => usb reset
> > > > > >>> resetting USB...
> > > > > >>> USB0: Core Release: 2.93a
> > > > > >>> scanning bus 0 for devices... unable to get descriptor, error 0
> > > > > >>> usb_new_device: Cannot read configuration, skipping device
> > > > > >>> 058f:6387 1 USB Device(s) found
> > > > > >>>
> > > > > >>> scanning usb for storage devices... 0 Storage
> > > > > >>> Device(s) found
> > > > > >>>
> > > > > >>> => dcache off
> > > > > >>> => usb reset
> > > > > >>> resetting USB...
> > > > > >>> USB0: Core Release: 2.93a
> > > > > >>> scanning bus 0 for devices... 2 USB Device(s) found
> > > > > >>>
> > > > > >>> scanning usb for storage devices... 1 Storage
> > > > > >>> Device(s) found
> > > > > >>>
> > > > > >>> If I revert this patch, my USB stick works as well.
> > > > > >>>
> > > > > >>> I am also aware that Stefan mentions that without this patch,
> > > > > >>> cache is not enabled at all. On the other hand, I cannot find
> > > > > >>> any obviously faulty behavior in the dwc2 driver, it does
> > > > > >>> flush_dcache_range()/invalidate_dcache_range() in the right
> > > > > >>> places.
> > > > > >>>
> > > > > >>> Any ideas please ?
> > > > > >>
> > > > > >> Perhaps its a timing related issue? As the code is executed
> > > > > >> faster with cache enabled. Just an idea - perhaps there is
> > > > > >> still some ugly code that doesn't do proper timer based loops /
> > > > > >> delays.
> > > > > >
> > > > > > I doubt that's not the case. If I disable cache just around the
> > > > > > hcdma bit in the driver (disable before the flush_dcache_range()
> > > > > > and enable after invalidate_dcache_range() in the driver), it
> > > > > > still fails.
> > > > >
> > > > > Did you check if this problem is perhaps also related to Dinh's L2
> > > > > cache patch:
> > > > >
> > > > > 8d8e13e1 arm: socfpga: enable data/inst prefetch and shared
> > > > > override in the L2
> > > > >
> > > > > ?
> > > >
> > > > Yes I did, but reverting this patch had no impact.
> > > >
> > > > > I just noticed, that here the L2 cache gets disabled and is not
> > > > > enabled again in function v7_outer_cache_enable(). This looks a
> > > > > bit suspicious.
> > > > >
> > > > > Dinh, did you perhaps miss to re-enable the L2 cache after the
> > > > > aux_ctrl register setup again?
> > > >
> > > > I guess we should pester Dinh now :-)
> > >
> > > I recompiled the latest source and it works for me.
> > > Here is the printout message.
> > > Wonder any modification against commit a55f28624e97e1e43ac?
> > >
> > >
> > > U-Boot 2015.10-08073-ga55f286 (Nov 11 2015 - 23:19:06 +0800)
> > >
> > > CPU: Altera SoCFPGA Platform
> > > FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
> > > BOOT: SD/MMC External Transceiver (1.8V)
> > >
> > > Watchdog enabled
> > >
> > > I2C: ready
> > > DRAM: 1 GiB
> > > MMC: SOCFPGA DWMMC: 0
> > > *** Warning - bad CRC, using default environment
> > >
> > > In: serial
> > > Out: serial
> > > Err: serial
> > > Model: Altera SOCFPGA Cyclone V SoC Development Kit
> > > Net:
> > > Error: ethernet at ff702000 address not set.
> > > No ethernet found.
> > > Hit any key to stop autoboot: 0
> > > => dcache
> > > Data (writethrough) Cache is ON
> > > => icache
> > > Instruction Cache is ON
> > > => usb start
> > > starting USB...
> > > USB0: Core Release: 2.93a
> > > scanning bus 0 for devices... 2 USB Device(s) found
> > >
> > > scanning usb for storage devices... 1 Storage Device(s) found
> > >
> > > => usb info
> > > 1: Hub, USB Revision 1.10
> > >
> > > - U-Boot Root Hub
> > > - Class: Hub
> > > - PacketSize: 8 Configurations: 1
> > > - Vendor: 0x0000 Product 0x0000 Version 0.0
> > >
> > > Configuration: 1
> > > - Interfaces: 1 Self Powered 0mA
> > >
> > > Interface: 0
> > > - Alternate Setting 0, Endpoints: 1
> > > - Class Hub
> > > - Endpoint 1 In Interrupt MaxPacket 2 Interval 255ms
> > >
> > > 2: Mass Storage, USB Revision 2.0
> > >
> > > - SanDisk SDDR-113 000000009412
> > > - Class: (from Interface) Mass Storage
> > > - PacketSize: 64 Configurations: 1
> > > - Vendor: 0x0781 Product 0xa7c1 Version 148.18
> > >
> > > Configuration: 1
> > > - Interfaces: 1 Bus Powered 500mA
> > >
> > > Interface: 0
> > > - Alternate Setting 0, Endpoints: 2
> > > - Class Mass Storage, Transp. SCSI, Bulk only
> > > - Endpoint 1 In Bulk MaxPacket 512
> > > - Endpoint 2 Out Bulk MaxPacket 512
> >
> > Yeah, that's because you're using high-quality USB sticks which leave
> > skid marks on the USB port. Now try with some dirt cheap USB 2.0 stick.
> >
> > 058f:6387 Alcor Micro Corp. Flash Drive
> >
> > The thing above is my absolute fav when it comes to testing corner cases:
> > http://www.intenso.de/produkte.php?kategorie=23&&produkt=1255723475
>
> It takes some amount of time for digging out a USB 2.0 stick :)
> But it still work for me as below.
> Let me check out the code and see any clue.
>
>
> 2: Mass Storage, USB Revision 2.0
> - USB DISK 2.0 0781076602A6
> - Class: (from Interface) Mass Storage
> - PacketSize: 64 Configurations: 1
> - Vendor: 0x13fe Product 0x1e00 Version 1.16
> Configuration: 1
> - Interfaces: 1 Bus Powered 200mA
> Interface: 0
> - Alternate Setting 0, Endpoints: 2
> - Class Mass Storage, Transp. SCSI, Bulk only
> - Endpoint 1 In Bulk MaxPacket 512
> - Endpoint 2 Out Bulk MaxPacket 512

I have another board where I cannot use UBI on QSPI NOR and reverting this
patch magically fixes things.