From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Mon, 9 Nov 2015 09:01:03 -0800 Subject: [U-Boot] [PATCH v2 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514 In-Reply-To: References: <1446719200-31044-1-git-send-email-yao.yuan@freescale.com> <1446719200-31044-4-git-send-email-yao.yuan@freescale.com> <563B9A51.7080603@freescale.com> Message-ID: <5640D14F.5080306@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 11/09/2015 01:30 AM, Yuan Yao-B46683 wrote: > Hi york, > > Is it for DDR4? > LS1021A doesn't use this file. LS1021A support both DDR3 and DDR4. DDR4 mode uses this driver, doesn't it? My concern is if the workaround is implemented in different places, it will be harder to maintain in future versions fix this erratum. Maybe moving the workaround out of DDR driver to SoC is not a bad idea. York > > Best Regards, > Yuan Yao > >> -----Original Message----- >> From: York Sun [mailto:yorksun at freescale.com] >> Sent: Friday, November 06, 2015 2:05 AM >> To: Yuan Yao-B46683 >> Cc: Wang Huan-B18965 ; u-boot at lists.denx.de >> Subject: Re: [PATCH v2 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum >> A008514 >> >> >> >> On 11/05/2015 02:26 AM, Yuan Yao wrote: >>> This is a workaround for hardware erratum. >>> Write the value of 63b2_0002h to EDDRTQCFG will optimal the memory >>> controller performance. >>> >>> The value: 63b2_0002h comes from the hardware team. >>> >>> Signed-off-by: Yuan Yao >>> --- >>> Changes in v2: >>> Rewrite the commit message to explain why and what this patch does. >>> --- >>> arch/arm/cpu/armv7/ls102xa/soc.c | 10 ++++++++++ >>> arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- >>> 2 files changed, 11 insertions(+), 1 deletion(-) >> >> Workaround for A008514 is already implemented in DDR driver >> drivers/ddr/fsl/fsl_ddr_gen4.c. Please see if you can merge your workaround >> into it. >> >> York >