[U-Boot] [PATCH 0/2] Add Xilinx Zynq boot.bin support

[U-Boot] [PATCH 0/2] Add Xilinx Zynq boot.bin support

[Nathan Rossi]

This patch series adds support for the 'zynqimage' type to mkimage for
the Xilinx Zynq platform. As well as adding make targets to generate
the boot.bin image file containing SPL by default.

Nathan Rossi (2):
  tools: zynqimage: Add Xilinx Zynq boot header generation to mkimage
  ARM: zynq: Add target for building bootable SPL image for Zynq

 Makefile             |   3 +
 common/image.c       |   1 +
 include/image.h      |   3 +-
 scripts/Makefile.spl |  11 +++
 tools/Makefile       |   1 +
 tools/zynqimage.c    | 259 +++++++++++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 277 insertions(+), 1 deletion(-)
 create mode 100644 tools/zynqimage.c

-- 
2.6.2

[U-Boot] [PATCH 1/2] tools: zynqimage: Add Xilinx Zynq boot header generation to mkimage

[Nathan Rossi]

As with other platforms vendors love to create their own boot header
formats. Xilinx is no different and for the Zynq platform/SoC there
exists the "boot.bin" which is read by the platforms bootrom. This
format is described to a useful extent within the Xilinx Zynq TRM.

This implementation adds support for the 'zynqimage' to mkimage. The
implementation only considers the most common boot header which is
un-encrypted and packed directly after the boot header itself (no
XIP, etc.). However this implementation does take into consideration the
other fields of the header for image dumping use cases (vector table and
register initialization).

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Tom Rini <trini@konsulko.com>
---
 common/image.c    |   1 +
 include/image.h   |   3 +-
 tools/Makefile    |   1 +
 tools/zynqimage.c | 259 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 263 insertions(+), 1 deletion(-)
 create mode 100644 tools/zynqimage.c

diff --git a/common/image.c b/common/image.c
index 85c4f39..c36927f 100644
--- a/common/image.c
+++ b/common/image.c
@@ -158,6 +158,7 @@ static const table_entry_t uimage_type[] = {
 	{	IH_TYPE_RKIMAGE,    "rkimage",    "Rockchip Boot Image" },
 	{	IH_TYPE_RKSD,       "rksd",       "Rockchip SD Boot Image" },
 	{	IH_TYPE_RKSPI,      "rkspi",      "Rockchip SPI Boot Image" },
+	{	IH_TYPE_ZYNQIMAGE,  "zynqimage",  "Xilinx Zynq Boot Image" },
 	{	-1,		    "",		  "",			},
 };
 
diff --git a/include/image.h b/include/image.h
index 08ae24a..299d6d2 100644
--- a/include/image.h
+++ b/include/image.h
@@ -248,8 +248,9 @@ struct lmb;
 #define IH_TYPE_RKIMAGE		23	/* Rockchip Boot Image		*/
 #define IH_TYPE_RKSD		24	/* Rockchip SD card		*/
 #define IH_TYPE_RKSPI		25	/* Rockchip SPI image		*/
+#define IH_TYPE_ZYNQIMAGE	26	/* Xilinx Zynq Boot Image */
 
-#define IH_TYPE_COUNT		26	/* Number of image types */
+#define IH_TYPE_COUNT		27	/* Number of image types */
 
 /*
  * Compression Types
diff --git a/tools/Makefile b/tools/Makefile
index 9082bda..9cfd80b 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -98,6 +98,7 @@ dumpimage-mkimage-objs := aisimage.o \
 			lib/sha256.o \
 			common/hash.o \
 			ublimage.o \
+			zynqimage.o \
 			$(LIBFDT_OBJS) \
 			$(RSA_OBJS-y)
 
diff --git a/tools/zynqimage.c b/tools/zynqimage.c
new file mode 100644
index 0000000..6d417d1
--- /dev/null
+++ b/tools/zynqimage.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * The following Boot Header format/structures and values are defined in the
+ * following documents:
+ *   * Xilinx Zynq-7000 Technical Reference Manual (Section 6.3)
+ *   * Xilinx Zynq-7000 Software Developers Guide (Appendix A.7 and A.8)
+ *
+ * Expected Header Size = 0x8C0
+ * Forced as 'little' endian, 32-bit words
+ *
+ *  0x  0 - Interrupt Table (8 words)
+ *  ...     (Default value = 0xeafffffe)
+ *  0x 1f
+ *  0x 20 - Width Detection
+ *         * DEFAULT_WIDTHDETECTION    0xaa995566
+ *  0x 24 - Image Identifier
+ *         * DEFAULT_IMAGEIDENTIFIER   0x584c4e58
+ *  0x 28 - Encryption
+ *         * 0x00000000 - None
+ *         * 0xa5c3c5a3 - eFuse
+ *         * 0x3a5c3c5a - bbRam
+ *  0x 2C - User Field
+ *  0x 30 - Image Offset
+ *  0x 34 - Image Size
+ *  0x 38 - Reserved (0x00000000) (according to spec)
+ *          * FSBL defines this field for Image Destination Address.
+ *  0x 3C - Image Load
+ *  0x 40 - Image Stored Size
+ *  0x 44 - Reserved (0x00000000) (according to spec)
+ *          * FSBL defines this field for QSPI configuration Data.
+ *  0x 48 - Checksum
+ *  0x 4c - Unused (21 words)
+ *  ...
+ *  0x 9c
+ *  0x a0 - Register Initialization, 256 Address and Data word pairs
+ *         * List is terminated with an address of 0xffffffff or
+ *  ...    * at the max number of entries
+ *  0x89c
+ *  0x8a0 - Unused (8 words)
+ *  ...
+ *  0x8bf
+ *  0x8c0 - Data/Image starts here or above
+ */
+
+#include "imagetool.h"
+#include "mkimage.h"
+#include <image.h>
+
+#define HEADER_INTERRUPT_DEFAULT (cpu_to_le32(0xeafffffe))
+#define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff))
+#define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566))
+#define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58))
+
+enum {
+	ENCRYPTION_EFUSE = 0xa5c3c5a3,
+	ENCRYPTION_BBRAM = 0x3a5c3c5a,
+	ENCRYPTION_NONE = 0x0,
+};
+
+struct zynq_reginit {
+	uint32_t address;
+	uint32_t data;
+};
+
+#define HEADER_INTERRUPT_VECTORS 8
+#define HEADER_REGINITS 256
+
+struct zynq_header {
+	uint32_t interrupt_vectors[HEADER_INTERRUPT_VECTORS]; /* 0x0 */
+	uint32_t width_detection; /* 0x20 */
+	uint32_t image_identifier; /* 0x24 */
+	uint32_t encryption; /* 0x28 */
+	uint32_t user_field; /* 0x2c */
+	uint32_t image_offset; /* 0x30 */
+	uint32_t image_size; /* 0x34 */
+	uint32_t __reserved1; /* 0x38 */
+	uint32_t image_load; /* 0x3c */
+	uint32_t image_stored_size; /* 0x40 */
+	uint32_t __reserved2; /* 0x44 */
+	uint32_t checksum; /* 0x48 */
+	uint32_t __reserved3[21]; /* 0x4c */
+	struct zynq_reginit register_init[HEADER_REGINITS]; /* 0xa0 */
+	uint32_t __reserved4[8]; /* 0x8a0 */
+};
+
+static struct zynq_header zynqimage_header;
+
+static uint32_t zynqimage_checksum(struct zynq_header *ptr)
+{
+	uint32_t checksum = 0;
+
+	if (ptr == NULL)
+		return 0;
+
+	checksum += le32_to_cpu(ptr->width_detection);
+	checksum += le32_to_cpu(ptr->image_identifier);
+	checksum += le32_to_cpu(ptr->encryption);
+	checksum += le32_to_cpu(ptr->user_field);
+	checksum += le32_to_cpu(ptr->image_offset);
+	checksum += le32_to_cpu(ptr->image_size);
+	checksum += le32_to_cpu(ptr->__reserved1);
+	checksum += le32_to_cpu(ptr->image_load);
+	checksum += le32_to_cpu(ptr->image_stored_size);
+	checksum += le32_to_cpu(ptr->__reserved2);
+	checksum = ~checksum;
+
+	return cpu_to_le32(checksum);
+}
+
+static void zynqimage_default_header(struct zynq_header *ptr)
+{
+	int i;
+
+	if (ptr == NULL)
+		return;
+
+	ptr->width_detection = HEADER_WIDTHDETECTION;
+	ptr->image_identifier = HEADER_IMAGEIDENTIFIER;
+	ptr->encryption = cpu_to_le32(ENCRYPTION_NONE);
+
+	/* Setup not-supported/constant/reserved fields */
+	for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++)
+		ptr->interrupt_vectors[i] = HEADER_INTERRUPT_DEFAULT;
+
+	ptr->interrupt_vectors[3] = 0x0;
+
+	for (i = 0; i < HEADER_REGINITS; i++) {
+		ptr->register_init[i].address = HEADER_REGINIT_NULL;
+		ptr->register_init[i].data = HEADER_REGINIT_NULL;
+	}
+
+	/*
+	 * Certain reserved fields are required to be set to 0, ensure they are
+	 * set as such.
+	 */
+	ptr->__reserved1 = 0x0;
+	ptr->__reserved2 = 0x0;
+}
+
+/* mkimage glue functions */
+static int zynqimage_verify_header(unsigned char *ptr, int image_size,
+		struct image_tool_params *params)
+{
+	struct zynq_header *zynqhdr = (struct zynq_header *)ptr;
+
+	if (image_size < sizeof(struct zynq_header))
+		return -1;
+
+	if (zynqhdr->width_detection != HEADER_WIDTHDETECTION)
+		return -1;
+	if (zynqhdr->image_identifier != HEADER_IMAGEIDENTIFIER)
+		return -1;
+
+	if (zynqimage_checksum(zynqhdr) != zynqhdr->checksum)
+		return -1;
+
+	return 0;
+}
+
+static void zynqimage_print_header(const void *ptr)
+{
+	struct zynq_header *zynqhdr = (struct zynq_header *)ptr;
+	int i;
+
+	printf("Image Type   : Xilinx Zynq Boot Image support\n");
+	printf("Image Offset : 0x%08x\n", le32_to_cpu(zynqhdr->image_offset));
+	printf("Image Size   : %lu bytes (%lu bytes packed)\n",
+	       (unsigned long)le32_to_cpu(zynqhdr->image_size),
+	       (unsigned long)le32_to_cpu(zynqhdr->image_stored_size));
+	printf("Image Load   : 0x%08x\n", le32_to_cpu(zynqhdr->image_load));
+	printf("User Field   : 0x%08x\n", le32_to_cpu(zynqhdr->user_field));
+	printf("Checksum     : 0x%08x\n", le32_to_cpu(zynqhdr->checksum));
+
+	for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++) {
+		if (zynqhdr->interrupt_vectors[i] == HEADER_INTERRUPT_DEFAULT)
+			continue;
+
+		printf("Modified Interrupt Vector Address [%d]: 0x%08x\n", i,
+		       le32_to_cpu(zynqhdr->interrupt_vectors[i]));
+	}
+
+	for (i = 0; i < HEADER_REGINITS; i++) {
+		if (zynqhdr->register_init[i].address == HEADER_REGINIT_NULL)
+			break;
+
+		if (i == 0)
+			printf("Custom Register Initialization:\n");
+
+		printf("    @ 0x%08x -> 0x%08x\n",
+		       le32_to_cpu(zynqhdr->register_init[i].address),
+		       le32_to_cpu(zynqhdr->register_init[i].data));
+	}
+}
+
+static int zynqimage_check_params(struct image_tool_params *params)
+{
+	if (!params)
+		return 0;
+
+	if (params->addr != 0x0) {
+		fprintf(stderr, "Error: Load Address cannot be specified.\n");
+		return -1;
+	}
+
+	/*
+	 * If the entry point is specified ensure it is 64 byte aligned.
+	 */
+	if (params->eflag && (params->ep % 64 != 0)) {
+		fprintf(stderr,
+			"Error: Entry Point must be aligned to a 64-byte boundary.\n");
+		return -1;
+	}
+
+	return !((params->lflag || params->dflag) ||
+			(params->dflag && params->eflag));
+}
+
+static int zynqimage_check_image_types(uint8_t type)
+{
+	if (type == IH_TYPE_ZYNQIMAGE)
+		return EXIT_SUCCESS;
+	return EXIT_FAILURE;
+}
+
+static void zynqimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+		struct image_tool_params *params)
+{
+	struct zynq_header *zynqhdr = (struct zynq_header *)ptr;
+	zynqimage_default_header(zynqhdr);
+
+	/* place image directly after header */
+	zynqhdr->image_offset =
+		cpu_to_le32((uint32_t)sizeof(struct zynq_header));
+	zynqhdr->image_size = cpu_to_le32((uint32_t)sbuf->st_size);
+	zynqhdr->image_stored_size = zynqhdr->image_size;
+	zynqhdr->image_load = 0x0;
+	if (params->eflag)
+		zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep);
+
+	zynqhdr->checksum = zynqimage_checksum(zynqhdr);
+}
+
+U_BOOT_IMAGE_TYPE(
+	zynqimage,
+	"Xilinx Zynq Boot Image support",
+	sizeof(struct zynq_header),
+	(void *)&zynqimage_header,
+	zynqimage_check_params,
+	zynqimage_verify_header,
+	zynqimage_print_header,
+	zynqimage_set_header,
+	NULL,
+	zynqimage_check_image_types,
+	NULL,
+	NULL
+);
-- 
2.6.2

[U-Boot] [PATCH 1/2] tools: zynqimage: Add Xilinx Zynq boot header generation to mkimage

[Nathan Rossi]

On Wed, Nov 11, 2015 at 9:46 PM, Nathan Rossi <nathan@nathanrossi.com> wrote:
> As with other platforms vendors love to create their own boot header
> formats. Xilinx is no different and for the Zynq platform/SoC there
> exists the "boot.bin" which is read by the platforms bootrom. This
> format is described to a useful extent within the Xilinx Zynq TRM.
>
> This implementation adds support for the 'zynqimage' to mkimage. The
> implementation only considers the most common boot header which is
> un-encrypted and packed directly after the boot header itself (no
> XIP, etc.). However this implementation does take into consideration the
> other fields of the header for image dumping use cases (vector table and
> register initialization).
>
> Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
> Cc: Michal Simek <michal.simek@xilinx.com>
> Cc: Tom Rini <trini@konsulko.com>
> ---
>  common/image.c    |   1 +
>  include/image.h   |   3 +-
>  tools/Makefile    |   1 +
>  tools/zynqimage.c | 259 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 263 insertions(+), 1 deletion(-)
>  create mode 100644 tools/zynqimage.c
>
> diff --git a/common/image.c b/common/image.c
> index 85c4f39..c36927f 100644
> --- a/common/image.c
> +++ b/common/image.c
> @@ -158,6 +158,7 @@ static const table_entry_t uimage_type[] = {
>         {       IH_TYPE_RKIMAGE,    "rkimage",    "Rockchip Boot Image" },
>         {       IH_TYPE_RKSD,       "rksd",       "Rockchip SD Boot Image" },
>         {       IH_TYPE_RKSPI,      "rkspi",      "Rockchip SPI Boot Image" },
> +       {       IH_TYPE_ZYNQIMAGE,  "zynqimage",  "Xilinx Zynq Boot Image" },
>         {       -1,                 "",           "",                   },
>  };
>
> diff --git a/include/image.h b/include/image.h
> index 08ae24a..299d6d2 100644
> --- a/include/image.h
> +++ b/include/image.h
> @@ -248,8 +248,9 @@ struct lmb;
>  #define IH_TYPE_RKIMAGE                23      /* Rockchip Boot Image          */
>  #define IH_TYPE_RKSD           24      /* Rockchip SD card             */
>  #define IH_TYPE_RKSPI          25      /* Rockchip SPI image           */
> +#define IH_TYPE_ZYNQIMAGE      26      /* Xilinx Zynq Boot Image */
>
> -#define IH_TYPE_COUNT          26      /* Number of image types */
> +#define IH_TYPE_COUNT          27      /* Number of image types */
>
>  /*
>   * Compression Types
> diff --git a/tools/Makefile b/tools/Makefile
> index 9082bda..9cfd80b 100644
> --- a/tools/Makefile
> +++ b/tools/Makefile
> @@ -98,6 +98,7 @@ dumpimage-mkimage-objs := aisimage.o \
>                         lib/sha256.o \
>                         common/hash.o \
>                         ublimage.o \
> +                       zynqimage.o \
>                         $(LIBFDT_OBJS) \
>                         $(RSA_OBJS-y)
>
> diff --git a/tools/zynqimage.c b/tools/zynqimage.c
> new file mode 100644
> index 0000000..6d417d1
> --- /dev/null
> +++ b/tools/zynqimage.c
> @@ -0,0 +1,259 @@
> +/*
> + * Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + *
> + * The following Boot Header format/structures and values are defined in the
> + * following documents:
> + *   * Xilinx Zynq-7000 Technical Reference Manual (Section 6.3)
> + *   * Xilinx Zynq-7000 Software Developers Guide (Appendix A.7 and A.8)
> + *
> + * Expected Header Size = 0x8C0
> + * Forced as 'little' endian, 32-bit words
> + *
> + *  0x  0 - Interrupt Table (8 words)
> + *  ...     (Default value = 0xeafffffe)
> + *  0x 1f
> + *  0x 20 - Width Detection
> + *         * DEFAULT_WIDTHDETECTION    0xaa995566
> + *  0x 24 - Image Identifier
> + *         * DEFAULT_IMAGEIDENTIFIER   0x584c4e58
> + *  0x 28 - Encryption
> + *         * 0x00000000 - None
> + *         * 0xa5c3c5a3 - eFuse
> + *         * 0x3a5c3c5a - bbRam
> + *  0x 2C - User Field
> + *  0x 30 - Image Offset
> + *  0x 34 - Image Size
> + *  0x 38 - Reserved (0x00000000) (according to spec)
> + *          * FSBL defines this field for Image Destination Address.
> + *  0x 3C - Image Load
> + *  0x 40 - Image Stored Size
> + *  0x 44 - Reserved (0x00000000) (according to spec)
> + *          * FSBL defines this field for QSPI configuration Data.
> + *  0x 48 - Checksum
> + *  0x 4c - Unused (21 words)
> + *  ...
> + *  0x 9c
> + *  0x a0 - Register Initialization, 256 Address and Data word pairs
> + *         * List is terminated with an address of 0xffffffff or
> + *  ...    * at the max number of entries
> + *  0x89c
> + *  0x8a0 - Unused (8 words)
> + *  ...
> + *  0x8bf
> + *  0x8c0 - Data/Image starts here or above
> + */
> +
> +#include "imagetool.h"
> +#include "mkimage.h"
> +#include <image.h>
> +
> +#define HEADER_INTERRUPT_DEFAULT (cpu_to_le32(0xeafffffe))
> +#define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff))
> +#define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566))
> +#define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58))
> +
> +enum {
> +       ENCRYPTION_EFUSE = 0xa5c3c5a3,
> +       ENCRYPTION_BBRAM = 0x3a5c3c5a,
> +       ENCRYPTION_NONE = 0x0,
> +};
> +
> +struct zynq_reginit {
> +       uint32_t address;
> +       uint32_t data;
> +};
> +
> +#define HEADER_INTERRUPT_VECTORS 8
> +#define HEADER_REGINITS 256
> +
> +struct zynq_header {
> +       uint32_t interrupt_vectors[HEADER_INTERRUPT_VECTORS]; /* 0x0 */
> +       uint32_t width_detection; /* 0x20 */
> +       uint32_t image_identifier; /* 0x24 */
> +       uint32_t encryption; /* 0x28 */
> +       uint32_t user_field; /* 0x2c */
> +       uint32_t image_offset; /* 0x30 */
> +       uint32_t image_size; /* 0x34 */
> +       uint32_t __reserved1; /* 0x38 */
> +       uint32_t image_load; /* 0x3c */
> +       uint32_t image_stored_size; /* 0x40 */
> +       uint32_t __reserved2; /* 0x44 */
> +       uint32_t checksum; /* 0x48 */
> +       uint32_t __reserved3[21]; /* 0x4c */
> +       struct zynq_reginit register_init[HEADER_REGINITS]; /* 0xa0 */
> +       uint32_t __reserved4[8]; /* 0x8a0 */
> +};
> +
> +static struct zynq_header zynqimage_header;
> +
> +static uint32_t zynqimage_checksum(struct zynq_header *ptr)
> +{
> +       uint32_t checksum = 0;
> +
> +       if (ptr == NULL)
> +               return 0;
> +
> +       checksum += le32_to_cpu(ptr->width_detection);
> +       checksum += le32_to_cpu(ptr->image_identifier);
> +       checksum += le32_to_cpu(ptr->encryption);
> +       checksum += le32_to_cpu(ptr->user_field);
> +       checksum += le32_to_cpu(ptr->image_offset);
> +       checksum += le32_to_cpu(ptr->image_size);
> +       checksum += le32_to_cpu(ptr->__reserved1);
> +       checksum += le32_to_cpu(ptr->image_load);
> +       checksum += le32_to_cpu(ptr->image_stored_size);
> +       checksum += le32_to_cpu(ptr->__reserved2);
> +       checksum = ~checksum;
> +
> +       return cpu_to_le32(checksum);
> +}
> +
> +static void zynqimage_default_header(struct zynq_header *ptr)
> +{
> +       int i;
> +
> +       if (ptr == NULL)
> +               return;
> +
> +       ptr->width_detection = HEADER_WIDTHDETECTION;
> +       ptr->image_identifier = HEADER_IMAGEIDENTIFIER;
> +       ptr->encryption = cpu_to_le32(ENCRYPTION_NONE);
> +
> +       /* Setup not-supported/constant/reserved fields */
> +       for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++)
> +               ptr->interrupt_vectors[i] = HEADER_INTERRUPT_DEFAULT;
> +
> +       ptr->interrupt_vectors[3] = 0x0;

Oops, accidentally left some test code in. Please ignore this line
when reviewing this patch, I will fix it up in a v2 after people have
had a chance to review this.

Thanks,
Nathan

> +
> +       for (i = 0; i < HEADER_REGINITS; i++) {
> +               ptr->register_init[i].address = HEADER_REGINIT_NULL;
> +               ptr->register_init[i].data = HEADER_REGINIT_NULL;
> +       }
> +
> +       /*
> +        * Certain reserved fields are required to be set to 0, ensure they are
> +        * set as such.
> +        */
> +       ptr->__reserved1 = 0x0;
> +       ptr->__reserved2 = 0x0;
> +}
> +
> +/* mkimage glue functions */
> +static int zynqimage_verify_header(unsigned char *ptr, int image_size,
> +               struct image_tool_params *params)
> +{
> +       struct zynq_header *zynqhdr = (struct zynq_header *)ptr;
> +
> +       if (image_size < sizeof(struct zynq_header))
> +               return -1;
> +
> +       if (zynqhdr->width_detection != HEADER_WIDTHDETECTION)
> +               return -1;
> +       if (zynqhdr->image_identifier != HEADER_IMAGEIDENTIFIER)
> +               return -1;
> +
> +       if (zynqimage_checksum(zynqhdr) != zynqhdr->checksum)
> +               return -1;
> +
> +       return 0;
> +}
> +
> +static void zynqimage_print_header(const void *ptr)
> +{
> +       struct zynq_header *zynqhdr = (struct zynq_header *)ptr;
> +       int i;
> +
> +       printf("Image Type   : Xilinx Zynq Boot Image support\n");
> +       printf("Image Offset : 0x%08x\n", le32_to_cpu(zynqhdr->image_offset));
> +       printf("Image Size   : %lu bytes (%lu bytes packed)\n",
> +              (unsigned long)le32_to_cpu(zynqhdr->image_size),
> +              (unsigned long)le32_to_cpu(zynqhdr->image_stored_size));
> +       printf("Image Load   : 0x%08x\n", le32_to_cpu(zynqhdr->image_load));
> +       printf("User Field   : 0x%08x\n", le32_to_cpu(zynqhdr->user_field));
> +       printf("Checksum     : 0x%08x\n", le32_to_cpu(zynqhdr->checksum));
> +
> +       for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++) {
> +               if (zynqhdr->interrupt_vectors[i] == HEADER_INTERRUPT_DEFAULT)
> +                       continue;
> +
> +               printf("Modified Interrupt Vector Address [%d]: 0x%08x\n", i,
> +                      le32_to_cpu(zynqhdr->interrupt_vectors[i]));
> +       }
> +
> +       for (i = 0; i < HEADER_REGINITS; i++) {
> +               if (zynqhdr->register_init[i].address == HEADER_REGINIT_NULL)
> +                       break;
> +
> +               if (i == 0)
> +                       printf("Custom Register Initialization:\n");
> +
> +               printf("    @ 0x%08x -> 0x%08x\n",
> +                      le32_to_cpu(zynqhdr->register_init[i].address),
> +                      le32_to_cpu(zynqhdr->register_init[i].data));
> +       }
> +}
> +
> +static int zynqimage_check_params(struct image_tool_params *params)
> +{
> +       if (!params)
> +               return 0;
> +
> +       if (params->addr != 0x0) {
> +               fprintf(stderr, "Error: Load Address cannot be specified.\n");
> +               return -1;
> +       }
> +
> +       /*
> +        * If the entry point is specified ensure it is 64 byte aligned.
> +        */
> +       if (params->eflag && (params->ep % 64 != 0)) {
> +               fprintf(stderr,
> +                       "Error: Entry Point must be aligned to a 64-byte boundary.\n");
> +               return -1;
> +       }
> +
> +       return !((params->lflag || params->dflag) ||
> +                       (params->dflag && params->eflag));
> +}
> +
> +static int zynqimage_check_image_types(uint8_t type)
> +{
> +       if (type == IH_TYPE_ZYNQIMAGE)
> +               return EXIT_SUCCESS;
> +       return EXIT_FAILURE;
> +}
> +
> +static void zynqimage_set_header(void *ptr, struct stat *sbuf, int ifd,
> +               struct image_tool_params *params)
> +{
> +       struct zynq_header *zynqhdr = (struct zynq_header *)ptr;
> +       zynqimage_default_header(zynqhdr);
> +
> +       /* place image directly after header */
> +       zynqhdr->image_offset =
> +               cpu_to_le32((uint32_t)sizeof(struct zynq_header));
> +       zynqhdr->image_size = cpu_to_le32((uint32_t)sbuf->st_size);
> +       zynqhdr->image_stored_size = zynqhdr->image_size;
> +       zynqhdr->image_load = 0x0;
> +       if (params->eflag)
> +               zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep);
> +
> +       zynqhdr->checksum = zynqimage_checksum(zynqhdr);
> +}
> +
> +U_BOOT_IMAGE_TYPE(
> +       zynqimage,
> +       "Xilinx Zynq Boot Image support",
> +       sizeof(struct zynq_header),
> +       (void *)&zynqimage_header,
> +       zynqimage_check_params,
> +       zynqimage_verify_header,
> +       zynqimage_print_header,
> +       zynqimage_set_header,
> +       NULL,
> +       zynqimage_check_image_types,
> +       NULL,
> +       NULL
> +);
> --
> 2.6.2
>

[U-Boot] [PATCH 1/2] tools: zynqimage: Add Xilinx Zynq boot header generation to mkimage

[Tom Rini]

On Wed, Nov 11, 2015 at 09:46:22PM +1000, Nathan Rossi wrote:

> As with other platforms vendors love to create their own boot header
> formats. Xilinx is no different and for the Zynq platform/SoC there
> exists the "boot.bin" which is read by the platforms bootrom. This
> format is described to a useful extent within the Xilinx Zynq TRM.
> 
> This implementation adds support for the 'zynqimage' to mkimage. The
> implementation only considers the most common boot header which is
> un-encrypted and packed directly after the boot header itself (no
> XIP, etc.). However this implementation does take into consideration the
> other fields of the header for image dumping use cases (vector table and
> register initialization).
> 
> Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
> Cc: Michal Simek <michal.simek@xilinx.com>
> Cc: Tom Rini <trini@konsulko.com>

Aside from the comment you already made,
Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 2/2] ARM: zynq: Add target for building bootable SPL image for Zynq

[Nathan Rossi]

Add a build target to generate 'boot.bin' which includes SPL. This is
used by the platforms BootROM to load SPL directly.

This change also conditionally changes what the 'boot.bin' target
generates depending on the SoC. Leaving the behaviour unchanged for the
AT91 targets.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Andreas Bie?mann <andreas.devel@googlemail.com>
Cc: Heiko Schocher <hs@denx.de>
---
 Makefile             |  3 +++
 scripts/Makefile.spl | 11 +++++++++++
 2 files changed, 14 insertions(+)

diff --git a/Makefile b/Makefile
index 61050ad..b7da462 100644
--- a/Makefile
+++ b/Makefile
@@ -1335,6 +1335,9 @@ spl/sunxi-spl.bin: spl/u-boot-spl
 spl/u-boot-spl-dtb.sfp: spl/u-boot-spl
 	@:
 
+spl/boot.bin: spl/u-boot-spl
+	@:
+
 tpl/u-boot-tpl.bin: tools prepare
 	$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all
 
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index dd235b9..b0d8551 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -116,6 +116,7 @@ MKIMAGEFLAGS_MLO.byteswap = -T omapimage -n byteswap -a $(CONFIG_SPL_TEXT_BASE)
 MLO MLO.byteswap: $(obj)/u-boot-spl.bin
 	$(call if_changed,mkimage)
 
+ifeq ($(CONFIG_SYS_SOC),"at91")
 MKIMAGEFLAGS_boot.bin = -T atmelimage
 
 ifeq ($(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER),y)
@@ -126,6 +127,12 @@ endif
 
 boot.bin: $(obj)/u-boot-spl.bin
 	$(call if_changed,mkimage)
+else
+MKIMAGEFLAGS_boot.bin = -T zynqimage
+
+spl/boot.bin: $(obj)/u-boot-spl-dtb.bin
+	$(call if_changed,mkimage)
+endif
 
 ALL-y	+= $(obj)/$(SPL_BIN).bin $(obj)/$(SPL_BIN).cfg
 
@@ -149,6 +156,10 @@ ifeq ($(CONFIG_SYS_SOC),"at91")
 ALL-y	+= boot.bin
 endif
 
+ifdef CONFIG_ARCH_ZYNQ
+ALL-y	+= $(obj)/boot.bin
+endif
+
 all:	$(ALL-y)
 
 quiet_cmd_cat = CAT     $@
-- 
2.6.2

[U-Boot] [PATCH 2/2] ARM: zynq: Add target for building bootable SPL image for Zynq

[Tom Rini]

On Wed, Nov 11, 2015 at 09:46:23PM +1000, Nathan Rossi wrote:

> Add a build target to generate 'boot.bin' which includes SPL. This is
> used by the platforms BootROM to load SPL directly.
> 
> This change also conditionally changes what the 'boot.bin' target
> generates depending on the SoC. Leaving the behaviour unchanged for the
> AT91 targets.
> 
> Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: Andreas Bie?mann <andreas.devel@googlemail.com>
> Cc: Heiko Schocher <hs@denx.de>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 0/2] Add Xilinx Zynq boot.bin support

[Michal Simek]

Hi guys,

On 11.11.2015 12:46, Nathan Rossi wrote:
> This patch series adds support for the 'zynqimage' type to mkimage for
> the Xilinx Zynq platform. As well as adding make targets to generate
> the boot.bin image file containing SPL by default.
> 
> Nathan Rossi (2):
>   tools: zynqimage: Add Xilinx Zynq boot header generation to mkimage
>   ARM: zynq: Add target for building bootable SPL image for Zynq
> 
>  Makefile             |   3 +
>  common/image.c       |   1 +
>  include/image.h      |   3 +-
>  scripts/Makefile.spl |  11 +++
>  tools/Makefile       |   1 +
>  tools/zynqimage.c    | 259 +++++++++++++++++++++++++++++++++++++++++++++++++++
>  6 files changed, 277 insertions(+), 1 deletion(-)
>  create mode 100644 tools/zynqimage.c
> 

Any comment on this one?

Nathan: Please send v2 if someone doesn't reply in day or two.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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[U-Boot] [PATCH 0/2] Add Xilinx Zynq boot.bin support

[Tom Rini]

On Mon, Nov 16, 2015 at 11:09:03AM +0100, Michal Simek wrote:
> Hi guys,
> 
> On 11.11.2015 12:46, Nathan Rossi wrote:
> > This patch series adds support for the 'zynqimage' type to mkimage for
> > the Xilinx Zynq platform. As well as adding make targets to generate
> > the boot.bin image file containing SPL by default.
> > 
> > Nathan Rossi (2):
> >   tools: zynqimage: Add Xilinx Zynq boot header generation to mkimage
> >   ARM: zynq: Add target for building bootable SPL image for Zynq
> > 
> >  Makefile             |   3 +
> >  common/image.c       |   1 +
> >  include/image.h      |   3 +-
> >  scripts/Makefile.spl |  11 +++
> >  tools/Makefile       |   1 +
> >  tools/zynqimage.c    | 259 +++++++++++++++++++++++++++++++++++++++++++++++++++
> >  6 files changed, 277 insertions(+), 1 deletion(-)
> >  create mode 100644 tools/zynqimage.c
> > 
> 
> Any comment on this one?

Reviewed and I figure this can come though the xilinx trees for v2.

-- 
Tom
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