From mboxrd@z Thu Jan 1 00:00:00 1970 From: Hans de Goede Date: Fri, 20 Nov 2015 16:40:47 +0100 Subject: [U-Boot] [PATCH] sunxi: clock: Set AHB1 clock frequency to 200MHz on Allwinner H3 In-Reply-To: <1447996068-12712-1-git-send-email-siarhei.siamashka@gmail.com> References: <1447996068-12712-1-git-send-email-siarhei.siamashka@gmail.com> Message-ID: <564F3EFF.3040606@redhat.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi, On 20-11-15 06:07, Siarhei Siamashka wrote: > The 3.4 kernel from the Allwinner SDK is clocking AHB1 at 200MHz > on Allwinner H3 and using PLL6 as the clock source (PLL6/3). > This can be verified by reading the value of the AHB1_APB1_CFG_REG > register via /dev/mem. It always reads as 0x3180 regardless of > the current cpufreq operating point. So this configuration should > be safe for use in U-Boot too. > > PLL6 also needs to be configured before it is used as the clock > source, according to the "CCU / Programming Guidelines" section > of the Allwinner manual. > > The current low AHB1 clock speed is limiting the USB transfer > speed when booting via FEL. This patch can increase the FEL USB > transfer speed from ~510 KB/s to ~950 KB/s. > > Signed-off-by: Siarhei Siamashka > --- > > This is intended to be used together with the Allwinner H3 patches > from Jens Kuske: > http://lists.denx.de/pipermail/u-boot/2015-November/234589.html Thanks, I've applied this patch to my tree, and it will be part of the next pull-req. Regards, Hans > > Allwinner A83T is likely using the same 200MHz AHB1 setup: > https://github.com/allwinner-zh/bootloader/blob/e5ceeca21188/basic_loader/bsp/bsp_for_a83/common/common.c#L101 > > I can successfully boot my A31s based tablet with 200MHz AHB1 clock > speed too. And this also speeds up FEL USB transfers. However I can't > check what kind of AHB1 configuration is used by the Android firmware > without rooting it first, which I wouldn't do at the moment. > > arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 6 ++++-- > arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 7 ++++++- > 2 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c > index 3ab3b31..916ee48 100644 > --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c > +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c > @@ -34,9 +34,11 @@ void clock_init_safe(void) > > clock_set_pll1(408000000); > > - writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); > - > writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); > + while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK)) > + ; > + > + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); > > writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); > writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); > diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h > index 584d351..09337a1 100644 > --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h > +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h > @@ -201,6 +201,7 @@ struct sunxi_ccm_reg { > #define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) > #define CCM_PLL6_CTRL_K_SHIFT 4 > #define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) > +#define CCM_PLL6_CTRL_LOCK (1 << 28) > > #define CCM_MIPI_PLL_CTRL_M_SHIFT 0 > #define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT) > @@ -219,7 +220,11 @@ struct sunxi_ccm_reg { > #define CCM_PLL11_CTRL_UPD (0x1 << 30) > #define CCM_PLL11_CTRL_EN (0x1 << 31) > > -#define AHB1_ABP1_DIV_DEFAULT 0x00002020 > +#if defined CONFIG_MACH_SUN8I_H3 > +#define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ > +#else > +#define AHB1_ABP1_DIV_DEFAULT 0x00002020 /* AHB1=AXI/4, APB1=AHB1/2 */ > +#endif > > #define AXI_GATE_OFFSET_DRAM 0 > >