[U-Boot] [PATCH] arm: socfpga: Repair SoCrates board

[Stefan Roese <sr@denx.de>]

Hi Marek,

On 20.11.2015 17:17, Marek Vasut wrote:
> This board was constantly parasiting on the CV SoCDK, so split it
> into it's own separate directory. Moreover, the board config was
> missing important bits, like simple-bus support in SPL, the DRAM
> configuration was incorrect and the DTS was also missing the pre
> reloc bits.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Dinh Nguyen <dinh.linux@gmail.com>
> ---
>   arch/arm/dts/socfpga_cyclone5_socrates.dts |   5 +
>   arch/arm/mach-socfpga/Kconfig              |   7 +
>   board/ebv/socrates/MAINTAINERS             |   6 +
>   board/ebv/socrates/Makefile                |   9 +
>   board/ebv/socrates/qts/iocsr_config.h      | 660 +++++++++++++++++++++++++++++
>   board/ebv/socrates/qts/pinmux_config.h     | 219 ++++++++++
>   board/ebv/socrates/qts/pll_config.h        |  85 ++++
>   board/ebv/socrates/qts/sdram_config.h      | 341 +++++++++++++++
>   board/ebv/socrates/socfpga.c               |  85 ++++
>   configs/socfpga_socrates_defconfig         |   3 +-
>   include/configs/socfpga_socrates.h         |  97 +++++
>   11 files changed, 1516 insertions(+), 1 deletion(-)
>   create mode 100644 board/ebv/socrates/MAINTAINERS
>   create mode 100644 board/ebv/socrates/Makefile
>   create mode 100644 board/ebv/socrates/qts/iocsr_config.h
>   create mode 100644 board/ebv/socrates/qts/pinmux_config.h
>   create mode 100644 board/ebv/socrates/qts/pll_config.h
>   create mode 100644 board/ebv/socrates/qts/sdram_config.h
>   create mode 100644 board/ebv/socrates/socfpga.c
>   create mode 100644 include/configs/socfpga_socrates.h
>
> diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
> index 6782691..05b935d 100644
> --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
> +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
> @@ -19,6 +19,10 @@
>   		device_type = "memory";
>   		reg = <0x0 0x40000000>; /* 1GB */
>   	};
> +
> +	soc {
> +		u-boot,dm-pre-reloc;
> +	};
>   };
>
>   &gmac1 {
> @@ -37,6 +41,7 @@
>
>   &mmc0 {
>   	status = "okay";
> +	u-boot,dm-pre-reloc;
>   };
>
>   &qspi {
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index a413ea4..f885703 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -22,6 +22,10 @@ config TARGET_SOCFPGA_DENX_MCVEVK
>   	bool "DENX MCVEVK (Cyclone V)"
>   	select TARGET_SOCFPGA_CYCLONE5
>
> +config TARGET_SOCFPGA_EBV_SOCRATES
> +	bool "EBV SoCrates (Cyclone V)"
> +	select TARGET_SOCFPGA_CYCLONE5
> +
>   config TARGET_SOCFPGA_TERASIC_DE0_NANO
>   	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
>   	select TARGET_SOCFPGA_CYCLONE5
> @@ -38,11 +42,13 @@ config SYS_BOARD
>   	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
>   	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
>   	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
> +	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
>
>   config SYS_VENDOR
>   	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
>   	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
>   	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
> +	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
>   	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
>   	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
>
> @@ -55,5 +61,6 @@ config SYS_CONFIG_NAME
>   	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
>   	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
>   	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
> +	default "socfpga_sockit" if TARGET_SOCFPGA_EBV_SOCRATES

	default "socfpga_socrates" if ... please

<snip>

> diff --git a/board/ebv/socrates/socfpga.c b/board/ebv/socrates/socfpga.c
> new file mode 100644
> index 0000000..a1dbc49
> --- /dev/null
> +++ b/board/ebv/socrates/socfpga.c
> @@ -0,0 +1,85 @@
> +/*
> + *  Copyright (C) 2012 Altera Corporation <www.altera.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/arch/reset_manager.h>
> +#include <asm/io.h>
> +
> +#include <usb.h>
> +#include <usb/s3c_udc.h>
> +#include <usb_mass_storage.h>
> +
> +#include <micrel.h>
> +#include <netdev.h>
> +#include <phy.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +void s_init(void) {}
> +
> +/*
> + * Miscellaneous platform dependent initialisations
> + */
> +int board_init(void)
> +{
> +	/* Address of boot parameters for ATAG (if ATAG is used) */
> +	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> +
> +	return 0;
> +}
> +
> +/*
> + * PHY configuration
> + */
> +#ifdef CONFIG_PHY_MICREL_KSZ9021
> +int board_phy_config(struct phy_device *phydev)
> +{
> +	int ret;
> +	/*
> +	 * These skew settings for the KSZ9021 ethernet phy is required for ethernet
> +	 * to work reliably on most flavors of cyclone5 boards.
> +	 */
> +	ret = ksz9021_phy_extended_write(phydev,
> +					 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
> +					 0x0);
> +	if (ret)
> +		return ret;
> +
> +	ret = ksz9021_phy_extended_write(phydev,
> +					 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
> +					 0x0);
> +	if (ret)
> +		return ret;
> +
> +	ret = ksz9021_phy_extended_write(phydev,
> +					 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
> +					 0xf0f0);
> +	if (ret)
> +		return ret;
> +
> +	if (phydev->drv->config)
> +		return phydev->drv->config(phydev);
> +
> +	return 0;
> +}
> +#endif

v2 of the SoCrates comes with a different PHY, IIRC. So we might
want to add some checking on the PHY model here at some time.

Other than that:

Reviewed-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan