* [U-Boot] [PATCH] sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
@ 2015-11-20 18:32 Hans de Goede
2015-11-21 15:48 ` Ian Campbell
0 siblings, 1 reply; 6+ messages in thread
From: Hans de Goede @ 2015-11-20 18:32 UTC (permalink / raw)
To: u-boot
According to the datasheets the max speed of AHB1 is 276 MHz, so
setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
and gives us a nice speed-up in certain workloads.
Suggested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 09337a1..5c76275 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -220,11 +220,7 @@ struct sunxi_ccm_reg {
#define CCM_PLL11_CTRL_UPD (0x1 << 30)
#define CCM_PLL11_CTRL_EN (0x1 << 31)
-#if defined CONFIG_MACH_SUN8I_H3
#define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
-#else
-#define AHB1_ABP1_DIV_DEFAULT 0x00002020 /* AHB1=AXI/4, APB1=AHB1/2 */
-#endif
#define AXI_GATE_OFFSET_DRAM 0
--
2.5.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH] sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
2015-11-20 18:32 [U-Boot] [PATCH] sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs Hans de Goede
@ 2015-11-21 15:48 ` Ian Campbell
2015-11-22 14:14 ` Chen-Yu Tsai
0 siblings, 1 reply; 6+ messages in thread
From: Ian Campbell @ 2015-11-21 15:48 UTC (permalink / raw)
To: u-boot
On Fri, 2015-11-20 at 19:32 +0100, Hans de Goede wrote:
> According to the datasheets the max speed of AHB1 is 276 MHz, so
> setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
> and gives us a nice speed-up in certain workloads.
>
> Suggested-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
I suppose you've tested this on at least one such board? In that case:
Acked-by: Ian Campbell <ijc@hellion.org.uk>
> ---
> arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> index 09337a1..5c76275 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> @@ -220,11 +220,7 @@ struct sunxi_ccm_reg {
> #define CCM_PLL11_CTRL_UPD (0x1 << 30)
> #define CCM_PLL11_CTRL_EN (0x1 << 31)
>
> -#if defined CONFIG_MACH_SUN8I_H3
> #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /*
> AHB1=PLL6/3,APB1=AHB1/2 */
> -#else
> -#define AHB1_ABP1_DIV_DEFAULT 0x00002020 /*
> AHB1=AXI/4, APB1=AHB1/2 */
> -#endif
>
> #define AXI_GATE_OFFSET_DRAM 0
>
^ permalink raw reply [flat|nested] 6+ messages in thread* [U-Boot] [PATCH] sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
2015-11-21 15:48 ` Ian Campbell
@ 2015-11-22 14:14 ` Chen-Yu Tsai
2015-11-22 15:40 ` Hans de Goede
0 siblings, 1 reply; 6+ messages in thread
From: Chen-Yu Tsai @ 2015-11-22 14:14 UTC (permalink / raw)
To: u-boot
On Sat, Nov 21, 2015 at 11:48 PM, Ian Campbell <ijc+uboot@hellion.org.uk> wrote:
> On Fri, 2015-11-20 at 19:32 +0100, Hans de Goede wrote:
>> According to the datasheets the max speed of AHB1 is 276 MHz, so
>> setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
>> and gives us a nice speed-up in certain workloads.
>>
>> Suggested-by: Chen-Yu Tsai <wens@csie.org>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>
> I suppose you've tested this on at least one such board? In that case:
> Acked-by: Ian Campbell <ijc@hellion.org.uk>
I've tested this on some of my boards. It works fine on my Hummingbird A31
and A23 Q8 tablet. However my Sinlinx SinA33 is giving me kernel Oops which
I haven't looked into yet.
ChenYu
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
2015-11-22 14:14 ` Chen-Yu Tsai
@ 2015-11-22 15:40 ` Hans de Goede
2015-11-23 6:47 ` Chen-Yu Tsai
0 siblings, 1 reply; 6+ messages in thread
From: Hans de Goede @ 2015-11-22 15:40 UTC (permalink / raw)
To: u-boot
Hi,
On 22-11-15 15:14, Chen-Yu Tsai wrote:
> On Sat, Nov 21, 2015 at 11:48 PM, Ian Campbell <ijc+uboot@hellion.org.uk> wrote:
>> On Fri, 2015-11-20 at 19:32 +0100, Hans de Goede wrote:
>>> According to the datasheets the max speed of AHB1 is 276 MHz, so
>>> setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
>>> and gives us a nice speed-up in certain workloads.
>>>
>>> Suggested-by: Chen-Yu Tsai <wens@csie.org>
>>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>>
>> I suppose you've tested this on at least one such board? In that case:
>> Acked-by: Ian Campbell <ijc@hellion.org.uk>
>
> I've tested this on some of my boards. It works fine on my Hummingbird A31
> and A23 Q8 tablet. However my Sinlinx SinA33 is giving me kernel Oops which
> I haven't looked into yet.
Works for me on a q8 A33 tablet. But lets investigate your oops before including
this in the next pull-req. Thanks for the testing!
Regards,
Hans
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
2015-11-22 15:40 ` Hans de Goede
@ 2015-11-23 6:47 ` Chen-Yu Tsai
2015-11-23 8:34 ` Ian Campbell
0 siblings, 1 reply; 6+ messages in thread
From: Chen-Yu Tsai @ 2015-11-23 6:47 UTC (permalink / raw)
To: u-boot
Hi,
On Sun, Nov 22, 2015 at 11:40 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 22-11-15 15:14, Chen-Yu Tsai wrote:
>>
>> On Sat, Nov 21, 2015 at 11:48 PM, Ian Campbell <ijc+uboot@hellion.org.uk>
>> wrote:
>>>
>>> On Fri, 2015-11-20 at 19:32 +0100, Hans de Goede wrote:
>>>>
>>>> According to the datasheets the max speed of AHB1 is 276 MHz, so
>>>> setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
>>>> and gives us a nice speed-up in certain workloads.
>>>>
>>>> Suggested-by: Chen-Yu Tsai <wens@csie.org>
>>>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>>>
>>>
>>> I suppose you've tested this on at least one such board? In that case:
>>> Acked-by: Ian Campbell <ijc@hellion.org.uk>
>>
>>
>> I've tested this on some of my boards. It works fine on my Hummingbird A31
>> and A23 Q8 tablet. However my Sinlinx SinA33 is giving me kernel Oops
>> which
>> I haven't looked into yet.
>
>
> Works for me on a q8 A33 tablet. But lets investigate your oops before
> including
> this in the next pull-req. Thanks for the testing!
I retested it with a proper clean build, and it works now. No idea what
the oops was about.
Also tested on my Sinlinx SinA31s. So it now works on all my sun6i generation
boards.
Tested-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs
2015-11-23 6:47 ` Chen-Yu Tsai
@ 2015-11-23 8:34 ` Ian Campbell
0 siblings, 0 replies; 6+ messages in thread
From: Ian Campbell @ 2015-11-23 8:34 UTC (permalink / raw)
To: u-boot
On Mon, 2015-11-23 at 14:47 +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Sun, Nov 22, 2015 at 11:40 PM, Hans de Goede <hdegoede@redhat.com>
> wrote:
> > Hi,
> >
> > On 22-11-15 15:14, Chen-Yu Tsai wrote:
> >>
> >> On Sat, Nov 21, 2015 at 11:48 PM, Ian Campbell <
> ijc+uboot at hellion.org.uk>
> >> wrote:
> >>>
> >>> On Fri, 2015-11-20 at 19:32 +0100, Hans de Goede wrote:
> >>>>
> >>>> According to the datasheets the max speed of AHB1 is 276 MHz, so
> >>>> setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
> >>>> and gives us a nice speed-up in certain workloads.
> >>>>
> >>>> Suggested-by: Chen-Yu Tsai <wens@csie.org>
> >>>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> >>>
> >>>
> >>> I suppose you've tested this on at least one such board? In that
> case:
> >>> Acked-by: Ian Campbell <ijc@hellion.org.uk>
> >>
> >>
> >> I've tested this on some of my boards. It works fine on my
> Hummingbird A31
> >> and A23 Q8 tablet. However my Sinlinx SinA33 is giving me kernel
> Oops
> >> which
> >> I haven't looked into yet.
> >
> >
> > Works for me on a q8 A33 tablet. But lets investigate your oops
> before
> > including
> > this in the next pull-req. Thanks for the testing!
>
> I retested it with a proper clean build, and it works now. No idea
> what
> the oops was about.
>
> Also tested on my Sinlinx SinA31s. So it now works on all my sun6i
> generation
> boards.
>
> Tested-by: Chen-Yu Tsai <wens@csie.org>
Good enough for me, my original Ack stands...
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-11-23 8:34 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2015-11-20 18:32 [U-Boot] [PATCH] sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCs Hans de Goede
2015-11-21 15:48 ` Ian Campbell
2015-11-22 14:14 ` Chen-Yu Tsai
2015-11-22 15:40 ` Hans de Goede
2015-11-23 6:47 ` Chen-Yu Tsai
2015-11-23 8:34 ` Ian Campbell
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