From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sinan Akman Date: Thu, 26 Nov 2015 11:03:56 -0500 Subject: [U-Boot] [PATCH 5/5] move the erratum_a008336_a008514 from general ddr file to soc file In-Reply-To: <1448524683-48444-5-git-send-email-yao.yuan@freescale.com> References: <1448524683-48444-1-git-send-email-yao.yuan@freescale.com> <1448524683-48444-5-git-send-email-yao.yuan@freescale.com> Message-ID: <56572D6C.70401@writeme.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Yuan On 26/11/15 02:58 AM, Yuan Yao wrote: > Both of the erratum:A008336 and A008514 are not apply to all the > soc like:LS1021A, LS1043A. nitpick : perhaps you could reword the commit message to make it a bit more clear. A suggestion : "As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file" > So it seems better to move those erratum codes form the general ddr > file to the private soc file. > > Signed-off-by: Yuan Yao > --- > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 37 +++++++++++++++++++++++++++++++++ > drivers/ddr/fsl/fsl_ddr_gen4.c | 34 ------------------------------ > 2 files changed, 37 insertions(+), 34 deletions(-) > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c > index 8896b70..738b113 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c Not exactly related to this patch but at this point we have : armv7/ls102xa armv8/fsl-layerscape I think ls102x is also considered a layerscape SoC and this is potentially confusing. Perhaps in another patch we can come up with better naming. Regards Sinan Akman > @@ -14,6 +14,41 @@ > DECLARE_GLOBAL_DATA_PTR; > > #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) > +/* > + * This erratum requires setting a value to eddrtqcr1 to > + * optimal the DDR performance. > + */ > +static void erratum_a008336(void) > +{ > + u32 *eddrtqcr1; > + > +#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 > +#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR > + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; > + out_le32(eddrtqcr1, 0x63b30002); > +#endif > +#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR > + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; > + out_le32(eddrtqcr1, 0x63b30002); > +#endif > +#endif > +} > + > +/* > + * This erratum requires a register write before being Memory > + * controller 3 being enabled. > + */ > +static void erratum_a008514(void) > +{ > + u32 *eddrtqcr1; > + > +#ifdef CONFIG_SYS_FSL_ERRATUM_A008514 > +#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR > + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; > + out_le32(eddrtqcr1, 0x63b20002); > +#endif > +#endif > +} > #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 > #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" > > @@ -118,6 +153,8 @@ void fsl_lsch3_early_init_f(void) > erratum_rcw_src(); > init_early_memctl_regs(); /* tighten IFC timing */ > erratum_a009203(); > + erratum_a008514(); > + erratum_a008336(); > } > > #elif defined(CONFIG_LS1043A) > diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c > index 50f4671..d7cbf34 100644 > --- a/drivers/ddr/fsl/fsl_ddr_gen4.c > +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c > @@ -48,10 +48,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, > u32 temp_sdram_cfg; > u32 total_gb_size_per_controller; > int timeout; > -#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ > - defined(CONFIG_SYS_FSL_ERRATUM_A008514) > - u32 *eddrtqcr1; > -#endif > #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 > u32 temp32, mr6; > u32 vref_seq1[3] = {0x80, 0x96, 0x16}; /* for range 1 */ > @@ -69,36 +65,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, > switch (ctrl_num) { > case 0: > ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; > -#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ > - defined(CONFIG_SYS_FSL_ERRATUM_A008514) > - eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; > -#endif > break; > #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) > case 1: > ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; > -#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ > - defined(CONFIG_SYS_FSL_ERRATUM_A008514) > - eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; > -#endif > break; > #endif > #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) > case 2: > ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; > -#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ > - defined(CONFIG_SYS_FSL_ERRATUM_A008514) > - eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; > -#endif > break; > #endif > #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) > case 3: > ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; > -#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ > - defined(CONFIG_SYS_FSL_ERRATUM_A008514) > - eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800; > -#endif > break; > #endif > default: > @@ -109,20 +89,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, > if (step == 2) > goto step2; > > -#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 > -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) > - /* A008336 only applies to general DDR controllers */ > - if ((ctrl_num == 0) || (ctrl_num == 1)) > -#endif > - ddr_out32(eddrtqcr1, 0x63b30002); > -#endif > -#ifdef CONFIG_SYS_FSL_ERRATUM_A008514 > -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) > - /* A008514 only applies to DP-DDR controler */ > - if (ctrl_num == 2) > -#endif > - ddr_out32(eddrtqcr1, 0x63b20002); > -#endif > if (regs->ddr_eor) > ddr_out32(&ddr->eor, regs->ddr_eor); > >