From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Mon, 30 Nov 2015 09:13:18 -0800 Subject: [U-Boot] [Patch V4 1/7] pci/layerscape: add support for LS1043A PCIe LUT register access In-Reply-To: <1447235920-46321-2-git-send-email-Qianyu.Gong@freescale.com> References: <1447235920-46321-1-git-send-email-Qianyu.Gong@freescale.com> <1447235920-46321-2-git-send-email-Qianyu.Gong@freescale.com> Message-ID: <565C83AE.6060302@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 11/11/2015 01:58 AM, Gong Qianyu wrote: > From: Mingkai Hu > > The endian and base address of PEX LUT register region is different > between Chassis 2 and Chassis 3, so move the base address definition > to chassis specific header file and add pex_lut_* functions to access > LUT register. > > Signed-off-by: Mingkai Hu > Signed-off-by: Gong Qianyu > --- > V4: > - Use #ifndef CONFIG_LS102XA instead of #ifdef CONFIG_FSL_LAYERSCAPE. > V3: > - No change. > V2: > - Fix compile errors for ls1021a. > > arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++ > arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 ++++ > arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++++ > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 8 ++++++++ > drivers/pci/pcie_layerscape.c | 14 +++++++------- > 5 files changed, 25 insertions(+), 7 deletions(-) Applied to fsl-qoriq master. Thanks. York