From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dinh Nguyen Date: Thu, 3 Dec 2015 13:56:34 -0600 Subject: [U-Boot] [PATCHv4 4/9] arm: socfpga: arria10: add misc functions for Arria10 In-Reply-To: <201512030347.51671.marex@denx.de> References: <1449084693-942-1-git-send-email-dinguyen@opensource.altera.com> <1449084693-942-5-git-send-email-dinguyen@opensource.altera.com> <201512030347.51671.marex@denx.de> Message-ID: <56609E72.5040500@opensource.altera.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 12/02/2015 08:47 PM, Marek Vasut wrote: > On Wednesday, December 02, 2015 at 08:31:28 PM, dinguyen at opensource.altera.com > wrote: >> From: Dinh Nguyen >> >> Add arch_early_init_r function. The Arria10 has a firewall protection >> around the SDRAM and OCRAM. These firewalls are to be disabled in order >> for U-Boot to function. >> >> Signed-off-by: Dinh Nguyen >> --- >> v4: be consistent and use #if->else throughout >> v3: >> s/reset_assert_all_peripherals_except_l4wd0_l4timer0/socfpga_per_reset_all >> use CONFIG_SOCFPGA_GEN5 >> v2: reuse misc functions from a5/c5 >> --- >> arch/arm/mach-socfpga/misc.c | 51 >> ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 >> insertions(+) >> >> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c >> index b110f5b..78774d5 100644 >> --- a/arch/arm/mach-socfpga/misc.c >> +++ b/arch/arm/mach-socfpga/misc.c >> @@ -15,6 +15,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -31,8 +32,15 @@ static struct socfpga_system_manager *sysmgr_regs = >> (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; >> static struct socfpga_reset_manager *reset_manager_base = >> (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; >> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) >> static struct nic301_registers *nic301_regs = >> (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; >> +#else >> +static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = >> + (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; >> +static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base = >> + (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; >> +#endif >> static struct scu_registers *scu_regs = >> (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; >> >> @@ -207,9 +215,14 @@ static int socfpga_fpga_id(const bool print_id) >> #if defined(CONFIG_DISPLAY_CPUINFO) >> int print_cpuinfo(void) >> { >> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) >> const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; >> puts("CPU: Altera SoCFPGA Platform\n"); >> socfpga_fpga_id(1); >> +#else >> + const u32 bsel = (readl(&sysmgr_regs->bootinfo) >> 12) & 0x7; > > Is the bsel meaning the same for both Gen5 and Gen10 ? If so, that's fine. > You can improve this code here by defining some bootinfo offset, 0 for gen5 > and 12 for gen10 and then you'd only need to ifdef the puts() and the invocation > of socfpga_fpga_id(); > > Can you send a subsequent patch for this ? > Yes, the bsel meaning is the same for Gen5 and Gen10. I'll send a follow up patch with Pavel's comment taken into consideration. Dinh