[U-Boot] [PATCH 1/1] fsl_qspi: Pet the watchdog while reading/writing

Alexander Stein
2015-11-25T09:33:53Z

On Wednesday 25 November 2015 02:20:53, Huan Wang wrote:
> [Alison Wang] I didn't meet any issue when using sf commands to write and
> read the serial flash.
>
> Hi, Alexander,
>
> Could you show me the detail commands and process when you meet
> such issue? Then I can try to reproduce on my board.

Yep, here is the output:
> U-Boot 2015.01-00671-g78773b9 (Nov 25 2015 - 10:28:50)
>
> CPU: Freescale LayerScape LS1021E, Version: 2.0, (0x87081120)
>
> Clock Configuration:
> CPU0(ARMV7):960 MHz,
> Bus:288 MHz, DDR:800 MHz (1600 MT/s data rate),
> Reset Configuration Word (RCW):
> 00000000: 0608000a 00000000 00000000 00000000
> 00000010: 70000000 08407922 40000a00 21046000
> 00000020: 00000000 00000000 00000000 0021ef00
> 00000030: 20024800 0888f340 00000000 00000000
> QSPI
> Watchdog enabled
> I2C: ready
> DRAM: Initializing DDR....
> Detected UDIMM Fixed DDR on board
> 512 MiB (DDR3, 16-bit, CL=11, ECC off)
> Using SERDES1 Protocol: 112 (0x70)
> MMC: FSL_SDHC: 0
> SF: Detected S25FL512S_256K with page size 512 Bytes, erase size 256 KiB,
> In: serial
> Out: serial
> Err: serial
> SF: Detected S25FL512S_256K with page size 512 Bytes, erase size 256 KiB,
> total 64 MiB SF: 262144 bytes @ 0x180000 Read: OK
> Firmware 'Microcode version 0.0.1 for LS1021a r1.0' for 1021 V1.0
> QE: uploading microcode 'Microcode for LS1021a r1.0' version 0.0.1
> SCSI: Net: eTSEC2 is in sgmii mode.
> eTSEC1 [PRIME], eTSEC2
> Hit any key to stop autoboot: 0
> => sf read 0x81040000 0x200000 0x400000
>
>
> U-Boot 2015.01-00671-g78773b9 (Nov 25 2015 - 10:28:50)
>
> CPU: Freescale LayerScape LS1021E, Version: 2.0, (0x87081120)
>
> Clock Configuration:
> CPU0(ARMV7):960 MHz,
> Bus:288 MHz, DDR:800 MHz (1600 MT/s data rate),
> Reset Configuration Word (RCW):
> 00000000: 0608000a 00000000 00000000 00000000
> 00000010: 70000000 08407922 40000a00 21046000
> 00000020: 00000000 00000000 00000000 0021ef00
> 00000030: 20024800 0888f340 00000000 00000000
> QSPI
> Watchdog enabled
> I2C: ready
> DRAM: Initializing DDR....
> Detected UDIMM Fixed DDR on board
> [...]
and so on...

The actual command which results in a watchdog reset is 'sf read 0x81040000 0x200000 0x400000'. Please note that this uses an external watchdog which is enabled by default and resets after ~1.5s. The command itself takes about 2s (taken from my watch).

Best regards,
Alexander
--
Dipl.-Inf. Alexander Stein
SYS TEC electronic GmbH
alexander.stein at systec-electronic.com

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