[U-Boot] [PATCH v2] mx6sxsabresd: Fix Ethernet PHY reset sequence

[U-Boot] [PATCH v2] mx6sxsabresd: Fix Ethernet PHY reset sequence

[Fabio Estevam]

From: Fabio Estevam <fabio.estevam@freescale.com>

Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is
registered") Ethernet is no longer functional.

This commit does not have an issue in itself, but it revelead a problem
with the Ethernet initialization.

Fix this by calling enable_fec_anatop_clock() earlier and also
by adding a 10ms reset delay as recommended in the AR8031 datasheet.

Suggested-by: J?rg Krause <joerg.krause@embedded.rocks>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1:
- Fix J?rg's email address

 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 3ee4662..56dc020 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -150,11 +150,15 @@ static int setup_fec(void)
 {
 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-	int reg;
+	int reg, ret;
 
 	/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
 
+	ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+	if (ret)
+		return ret;
+
 	imx_iomux_v3_setup_multiple_pads(phy_control_pads,
 					 ARRAY_SIZE(phy_control_pads));
 
@@ -163,14 +167,14 @@ static int setup_fec(void)
 
 	/* Reset AR8031 PHY */
 	gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
-	udelay(500);
+	mdelay(10);
 	gpio_set_value(IMX_GPIO_NR(2, 7), 1);
 
 	reg = readl(&anatop->pll_enet);
 	reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
 	writel(reg, &anatop->pll_enet);
 
-	return enable_fec_anatop_clock(0, ENET_125MHZ);
+	return 0;
 }
 
 int board_eth_init(bd_t *bis)
-- 
1.9.1

[U-Boot] [PATCH v2] mx6sxsabresd: Fix Ethernet PHY reset sequence

[Fabio Estevam]

Hi Stefano,

On Mon, Nov 23, 2015 at 4:18 PM, Fabio Estevam <festevam@gmail.com> wrote:
> From: Fabio Estevam <fabio.estevam@freescale.com>
>
> Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is
> registered") Ethernet is no longer functional.
>
> This commit does not have an issue in itself, but it revelead a problem
> with the Ethernet initialization.
>
> Fix this by calling enable_fec_anatop_clock() earlier and also
> by adding a 10ms reset delay as recommended in the AR8031 datasheet.
>
> Suggested-by: J?rg Krause <joerg.krause@embedded.rocks>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Any comments about this one?

Regards,

Fabio Estevam

[U-Boot] [PATCH v2] mx6sxsabresd: Fix Ethernet PHY reset sequence

[Stefano Babic]

On 04/12/2015 14:13, Fabio Estevam wrote:
> Hi Stefano,
> 
> On Mon, Nov 23, 2015 at 4:18 PM, Fabio Estevam <festevam@gmail.com> wrote:
>> From: Fabio Estevam <fabio.estevam@freescale.com>
>>
>> Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is
>> registered") Ethernet is no longer functional.
>>
>> This commit does not have an issue in itself, but it revelead a problem
>> with the Ethernet initialization.
>>
>> Fix this by calling enable_fec_anatop_clock() earlier and also
>> by adding a 10ms reset delay as recommended in the AR8031 datasheet.
>>
>> Suggested-by: J?rg Krause <joerg.krause@embedded.rocks>
>> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> 
> Any comments about this one?
> 
> Regards,
> 
> Fabio Estevam
> 

Fine with me, and I have not seen any other comments. I am applying it.

Reviewed-by: Stefano Babic <sbabic@denx.de>

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================