From mboxrd@z Thu Jan 1 00:00:00 1970 From: Michal Simek Date: Wed, 9 Dec 2015 09:11:41 +0100 Subject: [U-Boot] [PATCH] spi: zynq_qspi: Add configuration to disable LQSPI feature In-Reply-To: <1449585883-13332-1-git-send-email-nathan@nathanrossi.com> References: <1449585883-13332-1-git-send-email-nathan@nathanrossi.com> Message-ID: <5667E23D.5000002@monstr.eu> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 8.12.2015 15:44, Nathan Rossi wrote: > When the Zynq Boot ROM code loads the payload from QSPI it uses the > LQSPI feature of the QSPI device, however it does not clean up its > configuration before handing over to the payload which leaves the device > confgured to by-pass the standard non-linear operating mode. > > This ensures the Linear QSPI mode is disabled before re-enabling the > device. > > Signed-off-by: Nathan Rossi > Cc: Jagan Teki > Cc: Siva Durga Prasad Paladugu > Cc: Simon Glass > --- > drivers/spi/zynq_qspi.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c > index 5825c6d..b98663c 100644 > --- a/drivers/spi/zynq_qspi.c > +++ b/drivers/spi/zynq_qspi.c > @@ -30,6 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; > #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ > #define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ > #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ > +#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */ > > /* zynq qspi Transmit Data Register */ > #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */ > @@ -68,6 +69,9 @@ struct zynq_qspi_regs { > u32 txd1r; /* 0x80 */ > u32 txd2r; /* 0x84 */ > u32 txd3r; /* 0x88 */ > + u32 reserved1[5]; > + u32 lqspicfg; /* 0xA0 */ > + u32 lqspists; /* 0xA4 */ > }; > > /* zynq qspi platform data */ > @@ -143,6 +147,11 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) > ZYNQ_QSPI_CR_MSTREN_MASK; > writel(confr, ®s->cr); > > + /* Disable the LQSPI feature */ > + confr = readl(®s->lqspicfg); > + confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK; > + writel(confr, ®s->lqspicfg); > + > /* Enable SPI */ > writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr); > } > Applied to zynq tree. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 181 bytes Desc: OpenPGP digital signature URL: