[U-Boot] [PATCH 5/5][v5] drivers/crypto/fsl: fix endianness issue in RNG

York Sun
2015-12-15T01:12:00Z

On 12/08/2015 04:24 PM, Aneesh Bansal wrote:
> For Setting and clearing the bits in SEC Block registers
> sec_clrbits32() and sec_setbits32() are used which work as
> per endianness of CAAM block.
> So these must be used with SEC register address as argument.
> If the value is read in a local variable, then the functions
> will not behave correctly where endianness of CAAM and core is
> different.
>
> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
> CC: Alex Porosanu <alexandru.porosanu@freescale.com>
> ---
> Changes in v5: None
>
> Changes in v4: None
>
> Changes in v3: None
>
> Changes in v2: None (New Patch set created with an additional patch)

Applied to fsl-qoriq master. Awaiting upstream.

York