From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Tue, 15 Dec 2015 08:41:27 +0800 Subject: [U-Boot] [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3 In-Reply-To: <1446660203-18047-1-git-send-email-yorksun@freescale.com> References: <1446660203-18047-1-git-send-email-yorksun@freescale.com> Message-ID: <566F61B7.80201@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 11/05/2015 02:03 AM, York Sun wrote: > This patch set revises the DDR driver to support higher speed for DDR4 > under heavy load (two dual-rank DIMMs) for four-chipselect interleaving. > Single quad-rank DIMM is not supported yet. > > > York Sun (7): > driver/ddr/fsl: Update DDR4 RTT values > driver/ddr/fsl: Update DDR4 MR6 for Vref range > driver/ddr/fsl: Update MR5 RTT park > driver/ddr/fsl: Update workaround for A008511 for vref range > driver/ddr/fsl: Update timing config for heavy load > armv8/ls2085aqds: Update DDR settings for four chip-select case > armv8/ls2085ardb: Update DDR settings for four chip-select case > > board/freescale/ls2085aqds/ddr.c | 16 ++- > board/freescale/ls2085ardb/ddr.c | 16 ++- > drivers/ddr/fsl/ctrl_regs.c | 48 +++++++- > drivers/ddr/fsl/fsl_ddr_gen4.c | 22 ++-- > drivers/ddr/fsl/options.c | 237 +++++++++++++++++++++++++++++++++++++- > include/fsl_ddr_sdram.h | 9 ++ > 6 files changed, 325 insertions(+), 23 deletions(-) > Changed subject from ls2085a to ls2080a. Applied to fsl-qoriq master. Awaiting upstream. York