From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Sat, 19 Dec 2015 11:39:34 +0100 Subject: [U-Boot] [PATCH] arm: socfpga: Actually enable L2 cache In-Reply-To: <56752B81.9050901@denx.de> References: <1450504730-10190-1-git-send-email-marex@denx.de> <56752B81.9050901@denx.de> Message-ID: <567533E6.9090100@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 19.12.2015 11:03, Stefan Roese wrote: > On 19.12.2015 06:58, Marek Vasut wrote: >> The L2 cache was never enabled in the v7_outer_cache_enable(), fix >> this and enable the L2 cache. >> >> Signed-off-by: Marek Vasut >> Cc: Dinh Nguyen >> Cc: Chin Liang See >> --- >> arch/arm/mach-socfpga/misc.c | 7 +++++-- >> 1 file changed, 5 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c >> index b110f5b..621f5d9 100644 >> --- a/arch/arm/mach-socfpga/misc.c >> +++ b/arch/arm/mach-socfpga/misc.c >> @@ -54,14 +54,17 @@ void enable_caches(void) >> >> void v7_outer_cache_enable(void) >> { >> - /* disable the L2 cache */ >> - writel(0, &pl310->pl310_ctrl); >> + /* Disable the L2 cache */ >> + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); >> >> /* enable BRESP, instruction and data prefetch, full line of >> zeroes */ >> setbits_le32(&pl310->pl310_aux_ctrl, >> L310_AUX_CTRL_DATA_PREFETCH_MASK | >> L310_AUX_CTRL_INST_PREFETCH_MASK | >> L310_SHARED_ATT_OVERRIDE_ENABLE); >> + >> + /* Enable the L2 cache */ >> + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); > > Thanks Marek. I would be interested in some number here. Do you see > a bigger change in the performance (ethernet driver or dhrystone) > by enabling the L2 cache? And another comment. It might be necessary to disable the L2 cache when booting into Linux by providing the v7_outer_cache_enable() function. I noticed problems in Linux with MVEBU with the L2 cache still enabled. Thanks, Stefan