From: Stefan Roese <sr@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] arm: socfpga: Actually enable L2 cache
Date: Sun, 20 Dec 2015 03:39:41 +0100 [thread overview]
Message-ID: <567614ED.7070104@denx.de> (raw)
In-Reply-To: <201512191732.04949.marex@denx.de>
On 19.12.2015 17:32, Marek Vasut wrote:
> On Saturday, December 19, 2015 at 11:39:34 AM, Stefan Roese wrote:
>> On 19.12.2015 11:03, Stefan Roese wrote:
>>> On 19.12.2015 06:58, Marek Vasut wrote:
>>>> The L2 cache was never enabled in the v7_outer_cache_enable(), fix
>>>> this and enable the L2 cache.
>>>>
>>>> Signed-off-by: Marek Vasut <marex@denx.de>
>>>> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
>>>> Cc: Chin Liang See <clsee@altera.com>
>>>> ---
>>>>
>>>> arch/arm/mach-socfpga/misc.c | 7 +++++--
>>>> 1 file changed, 5 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
>>>> index b110f5b..621f5d9 100644
>>>> --- a/arch/arm/mach-socfpga/misc.c
>>>> +++ b/arch/arm/mach-socfpga/misc.c
>>>> @@ -54,14 +54,17 @@ void enable_caches(void)
>>>>
>>>> void v7_outer_cache_enable(void)
>>>> {
>>>>
>>>> - /* disable the L2 cache */
>>>> - writel(0, &pl310->pl310_ctrl);
>>>> + /* Disable the L2 cache */
>>>> + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
>>>>
>>>> /* enable BRESP, instruction and data prefetch, full line of
>>>>
>>>> zeroes */
>>>>
>>>> setbits_le32(&pl310->pl310_aux_ctrl,
>>>>
>>>> L310_AUX_CTRL_DATA_PREFETCH_MASK |
>>>> L310_AUX_CTRL_INST_PREFETCH_MASK |
>>>> L310_SHARED_ATT_OVERRIDE_ENABLE);
>>>>
>>>> +
>>>> + /* Enable the L2 cache */
>>>> + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
>>>
>>> Thanks Marek. I would be interested in some number here. Do you see
>>> a bigger change in the performance (ethernet driver or dhrystone)
>>> by enabling the L2 cache?
>>
>> And another comment. It might be necessary to disable the L2 cache
>> when booting into Linux by providing the v7_outer_cache_enable()
>> function. I noticed problems in Linux with MVEBU with the L2
>> cache still enabled.
>
> This is the v7_outer_cache_enable() function. Do you have anything else
> in mind ?
Yes, I meant v7_outer_cache_disable() of course.
Thanks,
Stefan
next prev parent reply other threads:[~2015-12-20 2:39 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-19 5:58 [U-Boot] [PATCH] arm: socfpga: Actually enable L2 cache Marek Vasut
2015-12-19 10:03 ` Stefan Roese
2015-12-19 10:39 ` Stefan Roese
2015-12-19 16:32 ` Marek Vasut
2015-12-20 2:39 ` Stefan Roese [this message]
2015-12-20 2:56 ` Marek Vasut
2015-12-19 16:31 ` Marek Vasut
2015-12-20 2:38 ` Stefan Roese
2015-12-20 2:57 ` Marek Vasut
2015-12-21 9:50 ` Chin Liang See
2015-12-21 10:09 ` Marek Vasut
2015-12-21 12:25 ` Chin Liang See
2015-12-21 14:19 ` Marek Vasut
2015-12-21 14:37 ` Chin Liang See
2015-12-21 14:39 ` Marek Vasut
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