[U-Boot] [PATCH 2/2] mx6cuboxi: Make Ethernet functional

[Troy Kisky <troy.kisky@boundarydevices.com>]

On 1/4/2016 9:36 AM, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@nxp.com>
> 
> Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is
> registered") Ethernet is no longer functional:
> 
> Booting from net ...                                                            
> FEC Waiting for PHY auto negotiation to complete......... TIMEOUT !             
> BOOTP broadcast 1                                                               
> BOOTP broadcast 2                                                               
> BOOTP broadcast 3                                                               
> BOOTP broadcast 4 
> 
> This commit does not have an issue in itself, but it revelead a problem
> with the Ethernet initialization.
>                                          
> Configure the AR8035 PHY in the same manner as done in mx6sabresd
> and wandboard, so that we can get a reliable Ethernet operation.  
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
> ---
>  board/solidrun/mx6cuboxi/mx6cuboxi.c | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
> index 20faffc..3bb7573 100644
> --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
> +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
> @@ -147,8 +147,33 @@ static void setup_iomux_enet(void)
>  	gpio_set_value(ETH_PHY_RESET, 1);
>  }
>  
> +static int mx6_rgmii_rework(struct phy_device *phydev)
> +{
> +	unsigned short val;
> +
> +	/* Enable AR8035 ouput a 125MHz clk from CLK_25M */
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
> +
> +	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
> +	val &= 0xffe3;
> +	val |= 0x18;


Except for clearing bit 2 (which is undocumented), this looks just like the default
implementation, which you are still calling below.

So, it looks like this subroutine can be replaced with an appropriate delay.
If bit 2 does matter, perhaps the default ar8035_config should be changed instead.



> +	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
> +
> +	/* introduce tx clock delay */
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
> +	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
> +	val |= 0x0100;
> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
> +
> +	return 0;
> +}
> +
>  int board_phy_config(struct phy_device *phydev)
>  {
> +	mx6_rgmii_rework(phydev);
> +
>  	if (phydev->drv->config)
>  		phydev->drv->config(phydev);
>  
> 


As a test perhaps you can call config twice instead of mx6_rgmii_rework
 if (phydev->drv->config) {
	phydev->drv->config(phydev);
	phydev->drv->config(phydev);
 }