[U-Boot] [PATCH 1/2] imx: mx7: default enable MDIO open drain

[U-Boot] [PATCH 1/2] imx: mx7: default enable MDIO open drain

[Peng Fan]

The management data input/output (MDIO) requires open-drain,
i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
this feature. So to TO1.1, need to enable open drain by setting
bits GPR0[8:7] for TO1.1.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/cpu/armv7/mx7/soc.c             | 20 ++++++++++++++++++++
 arch/arm/include/asm/arch-mx7/imx-regs.h |  2 ++
 2 files changed, 22 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
index c777922..1d8e470 100644
--- a/arch/arm/cpu/armv7/mx7/soc.c
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -130,6 +130,24 @@ static void init_csu(void)
 		writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
 }
 
+static void imx_enet_mdio_fixup(void)
+{
+	struct iomuxc_gpr_base_regs *gpr_regs =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/*
+	 * The management data input/output (MDIO) requires open-drain,
+	 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
+	 * this feature. So to TO1.1, need to enable open drain by setting
+	 * bits GPR0[8:7].
+	 */
+
+	if (soc_rev() >= CHIP_REV_1_1) {
+		setbits_le32(&gpr_regs->gpr[0],
+			     IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
+	}
+}
+
 int arch_cpu_init(void)
 {
 	init_aips();
@@ -138,6 +156,8 @@ int arch_cpu_init(void)
 	/* Disable PDE bit of WMCR register */
 	imx_set_wdog_powerdown(false);
 
+	imx_enet_mdio_fixup();
+
 #ifdef CONFIG_APBH_DMA
 	/* Start APBH DMA */
 	mxs_dma_init();
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index e28a807..58a25c7 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -272,6 +272,8 @@ struct src {
 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT    5
 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK     0x40u
 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT    6
+#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7)
+#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7
 /* GPR1 Bit Fields */
 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK    0x1u
 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT   0
-- 
2.6.2

[U-Boot] [PATCH 2/2] imx: mx7: fix the temperature checking for Rev1.1

[Peng Fan]

To TO1.0, we can not rely on finish bit to read temperature. But to
TO1.1, the issue was fixed by IC, we can rely on finish bit for
temperature reading for TO1.1.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Adrian Alonso <aalonso@freescale.com>
---
 drivers/thermal/imx_thermal.c | 30 +++++++++++++++++++++---------
 1 file changed, 21 insertions(+), 9 deletions(-)

diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index 09a3c52..45d5953 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -169,18 +169,30 @@ static int read_cpu_temperature(struct udevice *dev)
 	writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
 	writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set);
 
-	start = get_timer(0);
-	/* Wait max 100ms */
-	do {
-		/*
-		 * Since we can not rely on finish bit, use 1ms delay to get
-		 * temperature. From RM, 17us is enough to get data, but
-		 * to gurantee to get the data, delay 100ms here.
-		 */
+	if (soc_rev() >= CHIP_REV_1_1) {
+		/* make sure that the latest temp is valid */
+		while ((readl(&ccm_anatop->tempsense1) &
+		       TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK) == 0)
+			udelay(10000);
 		reg = readl(&ccm_anatop->tempsense1);
 		tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
 		       >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
-	} while (get_timer(0) < (start + 100));
+	} else {
+		start = get_timer(0);
+		/* Wait max 100ms */
+		do {
+			/*
+			 * Since we can not rely on finish bit, use 100ms
+			 * delay to get temperature. From RM, 17us is
+			 * enough to get data, but to gurantee to get
+			 * the data, delay 100ms here.
+			 */
+			reg = readl(&ccm_anatop->tempsense1);
+			tmp = (reg &
+			       TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
+			       >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
+		} while (get_timer(0) < (start + 100));
+	}
 
 	writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
 
-- 
2.6.2

[U-Boot] [PATCH 2/2] imx: mx7: fix the temperature checking for Rev1.1

[Peng Fan]

Hi Stefano,
On Mon, Jan 04, 2016 at 10:04:42AM +0100, Stefano Babic wrote:
>Hi Peng,
>
>On 04/01/2016 06:16, Peng Fan wrote:
>> To TO1.0, we can not rely on finish bit to read temperature. But to
>> TO1.1, the issue was fixed by IC, we can rely on finish bit for
>> temperature reading for TO1.1.
>> 
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> Cc: Stefano Babic <sbabic@denx.de>
>> Cc: Tim Harvey <tharvey@gateworks.com>
>> Cc: Fabio Estevam <fabio.estevam@freescale.com>
>> Cc: Adrian Alonso <aalonso@freescale.com>
>> ---
>>  drivers/thermal/imx_thermal.c | 30 +++++++++++++++++++++---------
>>  1 file changed, 21 insertions(+), 9 deletions(-)
>> 
>> diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
>> index 09a3c52..45d5953 100644
>> --- a/drivers/thermal/imx_thermal.c
>> +++ b/drivers/thermal/imx_thermal.c
>> @@ -169,18 +169,30 @@ static int read_cpu_temperature(struct udevice *dev)
>>  	writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
>>  	writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set);
>>  
>> -	start = get_timer(0);
>> -	/* Wait max 100ms */
>> -	do {
>> -		/*
>> -		 * Since we can not rely on finish bit, use 1ms delay to get
>> -		 * temperature. From RM, 17us is enough to get data, but
>> -		 * to gurantee to get the data, delay 100ms here.
>> -		 */
>> +	if (soc_rev() >= CHIP_REV_1_1) {
>> +		/* make sure that the latest temp is valid */
>> +		while ((readl(&ccm_anatop->tempsense1) &
>> +		       TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK) == 0)
>> +			udelay(10000);
>
>If 10ms is the minimal time, you should poll with a timer < 10mS, else
>you go out after 20mS. Processor is not doing anything, you can simply
>poll the register more often.

Will use timeout method. Thanks.

>
>>  		reg = readl(&ccm_anatop->tempsense1);
>>  		tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
>>  		       >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
>> -	} while (get_timer(0) < (start + 100));
>> +	} else {
>> +		start = get_timer(0);
>> +		/* Wait max 100ms */
>> +		do {
>> +			/*
>> +			 * Since we can not rely on finish bit, use 100ms
>> +			 * delay to get temperature. From RM, 17us is
>> +			 * enough to get data, but to gurantee to get
>> +			 * the data, delay 100ms here.
>> +			 */
>> +			reg = readl(&ccm_anatop->tempsense1);
>> +			tmp = (reg &
>> +			       TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
>> +			       >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
>> +		} while (get_timer(0) < (start + 100));
>> +	}
>
>This is nasty. You read the register, but you do not evaluate the result
>and you wait always 100mS. This has drawbacks for the boottime, because
>it is not so negligible. What is the reason to poll the register if you
>simply wait for timeout ?

Actually after temperature sensor finished sampling the temperature, it will
output a singal to a register, the finish bit in the register is for this.
But to TO1.0, we can not rely on finish bit, since it's value is not correct
because of IC logic issue. So I add 100ms here.
I may can use this way:
1. delay [xx]ms
2. read register value

Thanks,
Peng.

>
>Best regards,
>Stefano Babic
>
>-- 
>=====================================================================
>DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
>HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
>=====================================================================

[U-Boot] [PATCH 2/2] imx: mx7: fix the temperature checking for Rev1.1

[Stefano Babic]

Hi Peng,

On 04/01/2016 06:16, Peng Fan wrote:
> To TO1.0, we can not rely on finish bit to read temperature. But to
> TO1.1, the issue was fixed by IC, we can rely on finish bit for
> temperature reading for TO1.1.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Tim Harvey <tharvey@gateworks.com>
> Cc: Fabio Estevam <fabio.estevam@freescale.com>
> Cc: Adrian Alonso <aalonso@freescale.com>
> ---
>  drivers/thermal/imx_thermal.c | 30 +++++++++++++++++++++---------
>  1 file changed, 21 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
> index 09a3c52..45d5953 100644
> --- a/drivers/thermal/imx_thermal.c
> +++ b/drivers/thermal/imx_thermal.c
> @@ -169,18 +169,30 @@ static int read_cpu_temperature(struct udevice *dev)
>  	writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
>  	writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set);
>  
> -	start = get_timer(0);
> -	/* Wait max 100ms */
> -	do {
> -		/*
> -		 * Since we can not rely on finish bit, use 1ms delay to get
> -		 * temperature. From RM, 17us is enough to get data, but
> -		 * to gurantee to get the data, delay 100ms here.
> -		 */
> +	if (soc_rev() >= CHIP_REV_1_1) {
> +		/* make sure that the latest temp is valid */
> +		while ((readl(&ccm_anatop->tempsense1) &
> +		       TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK) == 0)
> +			udelay(10000);

If 10ms is the minimal time, you should poll with a timer < 10mS, else
you go out after 20mS. Processor is not doing anything, you can simply
poll the register more often.

>  		reg = readl(&ccm_anatop->tempsense1);
>  		tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
>  		       >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
> -	} while (get_timer(0) < (start + 100));
> +	} else {
> +		start = get_timer(0);
> +		/* Wait max 100ms */
> +		do {
> +			/*
> +			 * Since we can not rely on finish bit, use 100ms
> +			 * delay to get temperature. From RM, 17us is
> +			 * enough to get data, but to gurantee to get
> +			 * the data, delay 100ms here.
> +			 */
> +			reg = readl(&ccm_anatop->tempsense1);
> +			tmp = (reg &
> +			       TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
> +			       >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
> +		} while (get_timer(0) < (start + 100));
> +	}

This is nasty. You read the register, but you do not evaluate the result
and you wait always 100mS. This has drawbacks for the boottime, because
it is not so negligible. What is the reason to poll the register if you
simply wait for timeout ?

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 1/2] imx: mx7: default enable MDIO open drain

[Stefano Babic]

On 04/01/2016 06:16, Peng Fan wrote:
> The management data input/output (MDIO) requires open-drain,
> i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
> this feature. So to TO1.1, need to enable open drain by setting
> bits GPR0[8:7] for TO1.1.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---


Applied to u-boot-imx, thanks!

Best regards,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================