* [U-Boot] [PATCH v2 1/3] arm: at91/spl: mpddrc: add struct atmel_mpddrc_config
2015-12-01 2:47 [U-Boot] [PATCH v2 0/3] arm: at91/spl: add DDR3-SDRAM initialization support Wenyou Yang
@ 2015-12-01 2:47 ` Wenyou Yang
2015-12-01 2:47 ` [U-Boot] [PATCH v2 2/3] arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initialization Wenyou Yang
2015-12-01 2:48 ` [U-Boot] [PATCH v2 3/3] arm: at91/spl: mpddrc: use IP version to check configuration Wenyou Yang
2 siblings, 0 replies; 5+ messages in thread
From: Wenyou Yang @ 2015-12-01 2:47 UTC (permalink / raw)
To: u-boot
Add struct atmel_mpddrc_config to accommodate the mpddrc register
configurations, not using the mpddrc register map structure,
struct atmel_mpddrc, in order to increase readability and reduce
run-time memory use.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bie?mann <andreas.devel@googlemail.com>
---
Changes in v2:
- add Reviewed-by from Andreas.
arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 12 +++++++++++-
arch/arm/mach-at91/mpddrc.c | 2 +-
board/atmel/sama5d3_xplained/sama5d3_xplained.c | 4 ++--
board/atmel/sama5d3xek/sama5d3xek.c | 4 ++--
board/atmel/sama5d4_xplained/sama5d4_xplained.c | 4 ++--
board/atmel/sama5d4ek/sama5d4ek.c | 4 ++--
board/siemens/corvus/board.c | 4 ++--
7 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
index c6c8dda..47b4cd4 100644
--- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
+++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
@@ -8,6 +8,16 @@
#ifndef __ATMEL_MPDDRC_H__
#define __ATMEL_MPDDRC_H__
+struct atmel_mpddrc_config {
+ u32 mr;
+ u32 rtr;
+ u32 cr;
+ u32 tpr0;
+ u32 tpr1;
+ u32 tpr2;
+ u32 md;
+};
+
/*
* Only define the needed register in mpddr
* If other register needed, will add them later
@@ -26,7 +36,7 @@ struct atmel_mpddr {
int ddr2_init(const unsigned int base,
const unsigned int ram_address,
- const struct atmel_mpddr *mpddr);
+ const struct atmel_mpddrc_config *mpddr_value);
/* Bit field in mode register */
#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0
diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c
index 47e6e5a..9ba2a00 100644
--- a/arch/arm/mach-at91/mpddrc.c
+++ b/arch/arm/mach-at91/mpddrc.c
@@ -30,7 +30,7 @@ static int ddr2_decodtype_is_seq(u32 cr)
int ddr2_init(const unsigned int base,
const unsigned int ram_address,
- const struct atmel_mpddr *mpddr_value)
+ const struct atmel_mpddrc_config *mpddr_value)
{
const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
index 7a01149..7acb8d0 100644
--- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -143,7 +143,7 @@ void spl_board_init(void)
#endif
}
-static void ddr2_conf(struct atmel_mpddr *ddr2)
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
{
ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
@@ -185,7 +185,7 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
void mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- struct atmel_mpddr ddr2;
+ struct atmel_mpddrc_config ddr2;
ddr2_conf(&ddr2);
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index 7c95f33..0d824fc 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -402,7 +402,7 @@ void spl_board_init(void)
#endif
}
-static void ddr2_conf(struct atmel_mpddr *ddr2)
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
{
ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
@@ -444,7 +444,7 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
void mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- struct atmel_mpddr ddr2;
+ struct atmel_mpddrc_config ddr2;
ddr2_conf(&ddr2);
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index db45331..e2f33a3 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -346,7 +346,7 @@ void spl_board_init(void)
#endif
}
-static void ddr2_conf(struct atmel_mpddr *ddr2)
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
{
ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
@@ -384,7 +384,7 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
void mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- struct atmel_mpddr ddr2;
+ struct atmel_mpddrc_config ddr2;
ddr2_conf(&ddr2);
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
index 357b223..1799059 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -342,7 +342,7 @@ void spl_board_init(void)
#endif
}
-static void ddr2_conf(struct atmel_mpddr *ddr2)
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
{
ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
@@ -380,7 +380,7 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
void mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- struct atmel_mpddr ddr2;
+ struct atmel_mpddrc_config ddr2;
ddr2_conf(&ddr2);
diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
index 28985b8..38c0ca3 100644
--- a/board/siemens/corvus/board.c
+++ b/board/siemens/corvus/board.c
@@ -114,7 +114,7 @@ void spl_board_init(void)
}
#include <asm/arch/atmel_mpddrc.h>
-static void ddr2_conf(struct atmel_mpddr *ddr2)
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
{
ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
@@ -148,7 +148,7 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
void mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- struct atmel_mpddr ddr2;
+ struct atmel_mpddrc_config ddr2;
ddr2_conf(&ddr2);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 5+ messages in thread* [U-Boot] [PATCH v2 2/3] arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initialization
2015-12-01 2:47 [U-Boot] [PATCH v2 0/3] arm: at91/spl: add DDR3-SDRAM initialization support Wenyou Yang
2015-12-01 2:47 ` [U-Boot] [PATCH v2 1/3] arm: at91/spl: mpddrc: add struct atmel_mpddrc_config Wenyou Yang
@ 2015-12-01 2:47 ` Wenyou Yang
2016-01-26 15:15 ` Andreas Bießmann
2015-12-01 2:48 ` [U-Boot] [PATCH v2 3/3] arm: at91/spl: mpddrc: use IP version to check configuration Wenyou Yang
2 siblings, 1 reply; 5+ messages in thread
From: Wenyou Yang @ 2015-12-01 2:47 UTC (permalink / raw)
To: u-boot
The DDR3-SDRAM initialization sequence is implemented in
accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section
described in the SAMA5D2 datasheet.
Add registers and definitions of mpddrc controller, which is used
to support DDR3 devices.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
Changes in v2:
- remove comment accordingly after changing struct atmel_mpddr.
- remove some registers which have different definitions on
different SoCs to avoid confusion.
- remove whitespace error.
- rework commit log.
arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 85 ++++++++++++++++++++---
arch/arm/mach-at91/mpddrc.c | 88 ++++++++++++++++++++++++
2 files changed, 165 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
index 47b4cd4..47aae4d 100644
--- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
+++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
@@ -2,6 +2,9 @@
* Copyright (C) 2013 Atmel Corporation
* Bo Shen <voice.shen@atmel.com>
*
+ * Copyright (C) 2015 Atmel Corporation
+ * Wenyou Yang <wenyou.yang@atmel.com>
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -23,14 +26,35 @@ struct atmel_mpddrc_config {
* If other register needed, will add them later
*/
struct atmel_mpddr {
- u32 mr;
- u32 rtr;
- u32 cr;
- u32 tpr0;
- u32 tpr1;
- u32 tpr2;
- u32 reserved[2];
- u32 md;
+ u32 mr; /* 0x00: Mode Register */
+ u32 rtr; /* 0x04: Refresh Timer Register */
+ u32 cr; /* 0x08: Configuration Register */
+ u32 tpr0; /* 0x0c: Timing Parameter 0 Register */
+ u32 tpr1; /* 0x10: Timing Parameter 1 Register */
+ u32 tpr2; /* 0x14: Timing Parameter 2 Register */
+ u32 reserved; /* 0x18: Reserved */
+ u32 lpr; /* 0x1c: Low-power Register */
+ u32 md; /* 0x20: Memory Device Register */
+ u32 reserved1; /* 0x24: Reserved */
+ u32 lpddr23_lpr; /* 0x28: LPDDR2-LPDDR3 Low-power Register*/
+ u32 cal_mr4; /* 0x2c: Calibration and MR4 Register */
+ u32 tim_cal; /* 0x30: Timing Calibration Register */
+ u32 io_calibr; /* 0x34: IO Calibration */
+ u32 ocms; /* 0x38: OCMS Register */
+ u32 ocms_key1; /* 0x3c: OCMS KEY1 Register */
+ u32 ocms_key2; /* 0x40: OCMS KEY2 Register */
+ u32 conf_arbiter; /* 0x44: Configuration Arbiter Register */
+ u32 timeout; /* 0x48: Timeout Port 0/1/2/3 Register */
+ u32 req_port0123; /* 0x4c: Request Port 0/1/2/3 Register */
+ u32 req_port4567; /* 0x50: Request Port 4/5/6/7 Register */
+ u32 bdw_port0123; /* 0x54: Bandwidth Port 0/1/2/3 Register */
+ u32 bdw_port4567; /* 0x58: Bandwidth Port 4/5/6/7 Register */
+ u32 rd_data_path; /* 0x5c: Read Datapath Register */
+ u32 reserved2[33];
+ u32 wpmr; /* 0xe4: Write Protection Mode Register */
+ u32 wpsr; /* 0xe8: Write Protection Status Register */
+ u32 reserved3[4];
+ u32 version; /* 0xfc: IP version */
};
@@ -38,6 +62,9 @@ int ddr2_init(const unsigned int base,
const unsigned int ram_address,
const struct atmel_mpddrc_config *mpddr_value);
+int ddr3_init(const unsigned int ram_address,
+ const struct atmel_mpddrc_config *mpddr_value);
+
/* Bit field in mode register */
#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0
#define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1
@@ -120,9 +147,51 @@ int ddr2_init(const unsigned int base,
/* Bit field in Memory Device Register */
#define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3
+#define ATMEL_MPDDRC_MD_DDR3_SDRAM 0x4
+#define ATMEL_MPDDRC_MD_LPDDR3_SDRAM 0x5
#define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6
#define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4)
#define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4)
#define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4)
+/* Bit field in I/O Calibration Register */
+#define ATMEL_MPDDRC_IO_CALIBR_RDIV 0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_34_3 0x1
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_40 0x2
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48 0x3
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_60 0x4
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_80 0x6
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_120 0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_35 0x2
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_43 0x3
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 0x4
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_70 0x6
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_105 0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_37 0x2
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_44 0x3
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55 0x4
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73 0x6
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110 0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_37 0x2
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_44 0x3
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55 0x4
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73 0x6
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110 0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_TZQIO 0x7f
+#define ATMEL_MPDDRC_IO_CALIBR_TZQIO_(x) (((x) & 0x7f) << 8)
+
+#define ATMEL_MPDDRC_IO_CALIBR_EN_CALIB (0x1 << 4)
+
+/* Bit field in Read Data Path Register */
+#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING 0x3
+#define ATMEL_MPDDRC_RD_DATA_PATH_NO_SHIFT 0x0
+#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE 0x1
+#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE 0x2
+#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_THREE_CYCLE 0x3
+
#endif
diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c
index 9ba2a00..2b3a685 100644
--- a/arch/arm/mach-at91/mpddrc.c
+++ b/arch/arm/mach-at91/mpddrc.c
@@ -2,6 +2,9 @@
* Copyright (C) 2013 Atmel Corporation
* Bo Shen <voice.shen@atmel.com>
*
+ * Copyright (C) 2015 Atmel Corporation
+ * Wenyou Yang <wenyou.yang@atmel.com>
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -135,3 +138,88 @@ int ddr2_init(const unsigned int base,
return 0;
}
+
+int ddr3_init(const unsigned int ram_address,
+ const struct atmel_mpddrc_config *mpddr_value)
+{
+ struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+ u32 ba_off;
+
+ /* Compute bank offset according to NC in configuration register */
+ ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
+ if (ddr2_decodtype_is_seq(mpddr_value->cr))
+ ba_off += ((mpddr_value->cr &
+ ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
+
+ ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
+
+ /* Program the memory device type */
+ writel(mpddr_value->md, &mpddr->md);
+
+ /*
+ * Program features of the DDR3-SDRAM device and timing parameters
+ */
+ writel(mpddr_value->cr, &mpddr->cr);
+
+ writel(mpddr_value->tpr0, &mpddr->tpr0);
+ writel(mpddr_value->tpr1, &mpddr->tpr1);
+ writel(mpddr_value->tpr2, &mpddr->tpr2);
+
+ /* A NOP command is issued to the DDR3-SRAM */
+ atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
+
+ /* A pause of at least 500us must be observed before a single toggle. */
+ udelay(500);
+
+ /* A NOP command is issued to the DDR3-SDRAM */
+ atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
+
+ /*
+ * An Extended Mode Register Set (EMRS2) cycle is issued to choose
+ * between commercial or high temperature operations.
+ */
+ atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+ ram_address + (0x2 << ba_off));
+ /*
+ * Step 7: An Extended Mode Register Set (EMRS3) cycle is issued to set
+ * the Extended Mode Register to 0.
+ */
+ atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+ ram_address + (0x3 << ba_off));
+ /*
+ * An Extended Mode Register Set (EMRS1) cycle is issued to disable and
+ * to program O.D.S. (Output Driver Strength).
+ */
+ atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+ ram_address + (0x1 << ba_off));
+
+ /*
+ * Write a one to the DLL bit (enable DLL reset) in the MPDDRC
+ * Configuration Register.
+ */
+
+ /* A Mode Register Set (MRS) cycle is issued to reset DLL. */
+ atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
+
+ udelay(50);
+
+ /*
+ * A Calibration command (MRS) is issued to calibrate RTT and RON
+ * values for the Process Voltage Temperature (PVT).
+ */
+ atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_DEEP_CMD, ram_address);
+
+ /* A Normal Mode command is provided. */
+ atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
+
+ /* Perform a write access to any DDR3-SDRAM address. */
+ writel(0, ram_address);
+
+ /*
+ * Write the refresh rate into the COUNT field in the MPDDRC
+ * Refresh Timer Register (MPDDRC_RTR):
+ */
+ writel(mpddr_value->rtr, &mpddr->rtr);
+
+ return 0;
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 5+ messages in thread* [U-Boot] [PATCH v2 2/3] arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initialization
2015-12-01 2:47 ` [U-Boot] [PATCH v2 2/3] arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initialization Wenyou Yang
@ 2016-01-26 15:15 ` Andreas Bießmann
0 siblings, 0 replies; 5+ messages in thread
From: Andreas Bießmann @ 2016-01-26 15:15 UTC (permalink / raw)
To: u-boot
On 01.12.2015 03:47, Wenyou Yang wrote:
> The DDR3-SDRAM initialization sequence is implemented in
> accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section
> described in the SAMA5D2 datasheet.
>
> Add registers and definitions of mpddrc controller, which is used
> to support DDR3 devices.
>
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bie?mann <andreas.devel@googlemail.com>
> ---
>
> Changes in v2:
> - remove comment accordingly after changing struct atmel_mpddr.
> - remove some registers which have different definitions on
> different SoCs to avoid confusion.
> - remove whitespace error.
> - rework commit log.
>
> arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 85 ++++++++++++++++++++---
> arch/arm/mach-at91/mpddrc.c | 88 ++++++++++++++++++++++++
> 2 files changed, 165 insertions(+), 8 deletions(-)
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH v2 3/3] arm: at91/spl: mpddrc: use IP version to check configuration
2015-12-01 2:47 [U-Boot] [PATCH v2 0/3] arm: at91/spl: add DDR3-SDRAM initialization support Wenyou Yang
2015-12-01 2:47 ` [U-Boot] [PATCH v2 1/3] arm: at91/spl: mpddrc: add struct atmel_mpddrc_config Wenyou Yang
2015-12-01 2:47 ` [U-Boot] [PATCH v2 2/3] arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initialization Wenyou Yang
@ 2015-12-01 2:48 ` Wenyou Yang
2 siblings, 0 replies; 5+ messages in thread
From: Wenyou Yang @ 2015-12-01 2:48 UTC (permalink / raw)
To: u-boot
To remove the unnecessary #ifdef-endif, use the mpddrc IP version
to check whether or not the interleaved decoding type is supported.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bie?mann <andreas.devel@googlemail.com>
---
Changes in v2:
- add Reviewed-by from Andreas.
arch/arm/mach-at91/mpddrc.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c
index 2b3a685..3bb5b84 100644
--- a/arch/arm/mach-at91/mpddrc.c
+++ b/arch/arm/mach-at91/mpddrc.c
@@ -12,6 +12,8 @@
#include <asm/io.h>
#include <asm/arch/atmel_mpddrc.h>
+#define SAMA5D3_MPDDRC_VERSION 0x140
+
static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr,
int mode,
u32 ram_address)
@@ -22,11 +24,13 @@ static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr,
static int ddr2_decodtype_is_seq(u32 cr)
{
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
- defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
- if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
+ struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+ u16 version = readl(&mpddr->version) & 0xffff;
+
+ if ((version >= SAMA5D3_MPDDRC_VERSION) &&
+ (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
return 0;
-#endif
+
return 1;
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 5+ messages in thread