[U-Boot] [PATCH v4 07/13] MIPS: Add support for Microchip PIC32MZ[DA] SoC family.

[Daniel Schwierzeck <daniel.schwierzeck@gmail.com>]

Am 28.01.2016 um 11:00 schrieb Purna Chandra Mandal:
> Add Microchip PIC32MZ[DA] SoC family support.
> 
> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

> 
> ---
> 
> Changes in v4:
> - drop forcing DM_SERIAL, PIC32_SERIAL, PIC32_PINCTRL in mach-pic32/Kconfig
> - drop extra include
> - rename clock compatible to "pic32mzda-clk" from "pic32mzda_clk".
> - fix typo 'clock-cells' to '#clock-cells'
> 
> Changes in v3:
> - drop forcing CONFIG_MIPS_BOOT_* selection in mach-pic32/Kconfig
> - indent assembly instructions in delay slot
> - made GPIO-nodes child of pinctrl-node in devicetree
> - replace pic32_ioremap() with ioremap()
> 
> Changes in v2:
> - drop board_early_init_f
> - use macro LEAF(), END() for lowlevel_init
> - move initialization of board_init_f() argument to common start.S
> - move initdram() from board/microchip/ to mach-pic32/cpu.c
> - remove MIPS virtual address in favor physical one in dts file
> 
>  arch/mips/dts/pic32mzda.dtsi              | 153 ++++++++++++++++++++++++++++++
>  arch/mips/mach-pic32/Kconfig              |  17 +++-
>  arch/mips/mach-pic32/Makefile             |   2 +-
>  arch/mips/mach-pic32/cpu.c                | 143 ++++++++++++++++++++++++++++
>  arch/mips/mach-pic32/include/mach/pic32.h |   3 +
>  arch/mips/mach-pic32/lowlevel_init.S      |  27 ++++++
>  arch/mips/mach-pic32/reset.c              |  36 +++++++
>  7 files changed, 379 insertions(+), 2 deletions(-)
>  create mode 100644 arch/mips/dts/pic32mzda.dtsi
>  create mode 100644 arch/mips/mach-pic32/lowlevel_init.S
>  create mode 100644 arch/mips/mach-pic32/reset.c
> 
> diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
> new file mode 100644
> index 0000000..c67cfa9
> --- /dev/null
> +++ b/arch/mips/dts/pic32mzda.dtsi
> @@ -0,0 +1,153 @@
> +/*
> + * Copyright 2015 Microchip Technology, Inc.
> + * Purna Chandra Mandal, <purna.mandal@microchip.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/clock/microchip,clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include "skeleton.dtsi"
> +
> +/ {
> +	compatible = "microchip,pic32mzda", "microchip,pic32mz";
> +
> +	aliases {
> +		gpio0 = &gpioA;
> +		gpio1 = &gpioB;
> +		gpio2 = &gpioC;
> +		gpio3 = &gpioD;
> +		gpio4 = &gpioE;
> +		gpio5 = &gpioF;
> +		gpio6 = &gpioG;
> +		gpio7 = &gpioH;
> +		gpio8 = &gpioJ;
> +		gpio9 = &gpioK;
> +	};
> +
> +	cpus {
> +		cpu at 0 {
> +			compatible = "mips,mips14kc";
> +		};
> +	};
> +
> +	clock: clk at 1f801200 {
> +		compatible = "microchip,pic32mzda-clk";
> +		reg = <0x1f801200 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	uart1: serial at 1f822000 {
> +		compatible = "microchip,pic32mzda-uart";
> +		reg = <0x1f822000 0x50>;
> +		interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
> +		status = "disabled";
> +		clocks = <&clock PB2CLK>;
> +	};
> +
> +	uart2: serial at 1f822200 {
> +		compatible = "microchip,pic32mzda-uart";
> +		reg = <0x1f822200 0x50>;
> +		interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&clock PB2CLK>;
> +		status = "disabled";
> +	};
> +
> +	uart6: serial at 1f822a00 {
> +		compatible = "microchip,pic32mzda-uart";
> +		reg = <0x1f822a00 0x50>;
> +		interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&clock PB2CLK>;
> +		status = "disabled";
> +	};
> +
> +	evic: interrupt-controller at 1f810000 {
> +		compatible = "microchip,pic32mzda-evic";
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		reg = <0x1f810000 0x1000>;
> +	};
> +
> +	pinctrl: pinctrl at 1f801400 {
> +		compatible = "microchip,pic32mzda-pinctrl";
> +		reg = <0x1f801400 0x100>, /* in  */
> +		      <0x1f801500 0x200>, /* out */
> +		      <0x1f860000 0xa00>; /* port */
> +		reg-names = "ppsin","ppsout","port";
> +		status = "disabled";
> +
> +		ranges = <0 0x1f860000 0xa00>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		gpioA: gpio0 at 0 {
> +			compatible = "microchip,pic32mzda-gpio";
> +			reg = <0x000 0x48>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +		};
> +
> +		gpioB: gpio1 at 100 {
> +			compatible = "microchip,pic32mzda-gpio";
> +			reg = <0x100 0x48>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +		};
> +
> +		gpioC: gpio2 at 200 {
> +			compatible = "microchip,pic32mzda-gpio";
> +			reg = <0x200 0x48>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +		};
> +
> +		gpioD: gpio3 at 300 {
> +			compatible = "microchip,pic32mzda-gpio";
> +			reg = <0x300 0x48>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +		};
> +
> +		gpioE: gpio4 at 400 {
> +			compatible = "microchip,pic32mzda-gpio";
> +			reg = <0x400 0x48>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +		};
> +
> +		gpioF: gpio5 at 500 {
> +			compatible = "microchip,pic32mzda-gpio";
> +			reg = <0x500 0x48>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +		};
> +
> +		gpioG: gpio6 at 600 {
> +			compatible = "microchip,pic32mzda-gpio";
> +			reg = <0x600 0x48>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +		};
> +
> +		gpioH: gpio7 at 700 {
> +			compatible = "microchip,pic32mzda-gpio";
> +			reg = <0x700 0x48>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +		};
> +
> +		gpioJ: gpio8 at 800 {
> +			compatible = "microchip,pic32mzda-gpio";
> +			reg = <0x800 0x48>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +		};
> +
> +		gpioK: gpio9 at 900 {
> +			compatible = "microchip,pic32mzda-gpio";
> +			reg = <0x900 0x48>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +		};
> +	};
> +};
> diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
> index c1cc5e3..f636266 100644
> --- a/arch/mips/mach-pic32/Kconfig
> +++ b/arch/mips/mach-pic32/Kconfig
> @@ -2,6 +2,21 @@ menu "Microchip PIC32 platforms"
>  	depends on MACH_PIC32
>  
>  config SYS_SOC
> -	default "none"
> +	default "pic32mzda" if SOC_PIC32MZDA
> +
> +choice
> +	prompt "PIC32 SoC select"
> +
> +config SOC_PIC32MZDA
> +	bool "Microchip PIC32MZ[DA] family"
> +	select SUPPORTS_LITTLE_ENDIAN
> +	select SUPPORTS_CPU_MIPS32_R1
> +	select SUPPORTS_CPU_MIPS32_R2
> +	select MIPS_L1_CACHE_SHIFT_4
> +	select SYS_MIPS_CACHE_INIT_RAM_LOAD
> +	help
> +	  This supports Microchip PIC32MZ[DA] family of microcontrollers.
> +
> +endchoice
>  
>  endmenu
> diff --git a/arch/mips/mach-pic32/Makefile b/arch/mips/mach-pic32/Makefile
> index cb42607..e321e65 100644
> --- a/arch/mips/mach-pic32/Makefile
> +++ b/arch/mips/mach-pic32/Makefile
> @@ -4,4 +4,4 @@
>  # SPDX-License-Identifier:      GPL-2.0+
>  #
>  
> -obj-y = cpu.o
> +obj-y = cpu.o lowlevel_init.o reset.o
> \ No newline at end of file
> diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
> index 58fd3ab..f2ee911 100644
> --- a/arch/mips/mach-pic32/cpu.c
> +++ b/arch/mips/mach-pic32/cpu.c
> @@ -6,8 +6,151 @@
>   *
>   */
>  #include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <mach/pic32.h>
> +#include <mach/ddr.h>
> +#include <dt-bindings/clock/microchip,clock.h>
>  
> +/* Flash prefetch */
> +#define PRECON          0x00
> +
> +/* Flash ECCCON */
> +#define ECC_MASK	0x03
> +#define ECC_SHIFT	4
> +
> +#define CLK_MHZ(x)	((x) / 1000000)
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static ulong clk_get_cpu_rate(void)
> +{
> +	int ret;
> +	struct udevice *dev;
> +
> +	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
> +	if (ret) {
> +		panic("uclass-clk: device not found\n");
> +		return 0;
> +	}
> +
> +	return clk_get_rate(dev);
> +}
> +
> +/* initialize prefetch module related to cpu_clk */
> +static void prefetch_init(void)
> +{
> +	struct pic32_reg_atomic *regs;
> +	const void __iomem *base;
> +	int v, nr_waits;
> +	ulong rate;
> +
> +	/* cpu frequency in MHZ */
> +	rate = clk_get_cpu_rate() / 1000000;
> +
> +	/* get flash ECC type */
> +	base = pic32_get_syscfg_base();
> +	v = (readl(base + CFGCON) >> ECC_SHIFT) & ECC_MASK;
> +
> +	if (v < 2) {
> +		if (rate < 66)
> +			nr_waits = 0;
> +		else if (rate < 133)
> +			nr_waits = 1;
> +		else
> +			nr_waits = 2;
> +	} else {
> +		if (rate <= 83)
> +			nr_waits = 0;
> +		else if (rate <= 166)
> +			nr_waits = 1;
> +		else
> +			nr_waits = 2;
> +	}
> +
> +	regs = ioremap(PREFETCH_BASE + PRECON, sizeof(*regs));
> +	writel(nr_waits, &regs->raw);
> +
> +	/* Enable prefetch for all */
> +	writel(0x30, &regs->set);
> +	iounmap(regs);
> +}
> +
> +/* arch specific CPU init after DM */
> +int arch_cpu_init_dm(void)
> +{
> +	/* flash prefetch */
> +	prefetch_init();
> +	return 0;
> +}
> +
> +/* Un-gate DDR2 modules (gated by default) */
> +static void ddr2_pmd_ungate(void)
> +{
> +	void __iomem *regs;
> +
> +	regs = pic32_get_syscfg_base();
> +	writel(0, regs + PMD7);
> +}
> +
> +/* initialize the DDR2 Controller and DDR2 PHY */
>  phys_size_t initdram(int board_type)
>  {
> +	ddr2_pmd_ungate();
> +	ddr2_phy_init();
> +	ddr2_ctrl_init();
> +	return ddr2_calculate_size();
> +}
> +
> +int misc_init_r(void)
> +{
> +	set_io_port_base(0);
> +	return 0;
> +}
> +
> +#ifdef CONFIG_DISPLAY_BOARDINFO
> +const char *get_core_name(void)
> +{
> +	u32 proc_id;
> +	const char *str;
> +
> +	proc_id = read_c0_prid();
> +	switch (proc_id) {
> +	case 0x19e28:
> +		str = "PIC32MZ[DA]";
> +		break;
> +	default:
> +		str = "UNKNOWN";
> +	}
> +
> +	return str;
> +}
> +#endif
> +#ifdef CONFIG_CMD_CLK
> +int soc_clk_dump(void)
> +{
> +	int i, ret;
> +	struct udevice *dev;
> +
> +	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
> +	if (ret) {
> +		printf("clk-uclass not found\n");
> +		return ret;
> +	}
> +
> +	printf("PLL Speed: %lu MHz\n",
> +	       CLK_MHZ(clk_get_periph_rate(dev, PLLCLK)));
> +	printf("CPU Speed: %lu MHz\n", CLK_MHZ(clk_get_rate(dev)));
> +	printf("MPLL Speed: %lu MHz\n",
> +	       CLK_MHZ(clk_get_periph_rate(dev, MPLL)));
> +
> +	for (i = PB1CLK; i <= PB7CLK; i++)
> +		printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
> +		       CLK_MHZ(clk_get_periph_rate(dev, i)));
> +
> +	for (i = REF1CLK; i <= REF5CLK; i++)
> +		printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
> +		       CLK_MHZ(clk_get_periph_rate(dev, i)));
>  	return 0;
>  }
> +#endif
> diff --git a/arch/mips/mach-pic32/include/mach/pic32.h b/arch/mips/mach-pic32/include/mach/pic32.h
> index 7e41810..16bfacf 100644
> --- a/arch/mips/mach-pic32/include/mach/pic32.h
> +++ b/arch/mips/mach-pic32/include/mach/pic32.h
> @@ -73,4 +73,7 @@ static inline void __iomem *pic32_get_syscfg_base(void)
>  	return (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE);
>  }
>  
> +/* Core */
> +const char *get_core_name(void);
> +
>  #endif	/* __PIC32_REGS_H__ */
> diff --git a/arch/mips/mach-pic32/lowlevel_init.S b/arch/mips/mach-pic32/lowlevel_init.S
> new file mode 100644
> index 0000000..e37bebb
> --- /dev/null
> +++ b/arch/mips/mach-pic32/lowlevel_init.S
> @@ -0,0 +1,27 @@
> +/*
> + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + *
> +*/
> +
> +#include <config.h>
> +#include <asm/regdef.h>
> +#include <asm/mipsregs.h>
> +#include <asm/asm.h>
> +
> +LEAF(lowlevel_init)
> +	/*
> +	 * Establish Cause
> +	 * (set IV bit)
> +	 */
> +	li	t1, 0x00800000
> +	mtc0	t1, CP0_CAUSE
> +
> +	/* Establish Wired (and Random) */
> +	mtc0	zero, CP0_WIRED
> +	 nop
> +
> +	jr	ra
> +	 nop
> +	END(lowlevel_init)
> diff --git a/arch/mips/mach-pic32/reset.c b/arch/mips/mach-pic32/reset.c
> new file mode 100644
> index 0000000..66c6833
> --- /dev/null
> +++ b/arch/mips/mach-pic32/reset.c
> @@ -0,0 +1,36 @@
> +/*
> + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + *
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <mach/pic32.h>
> +
> +/* SYSKEY */
> +#define UNLOCK_KEY1	0xaa996655
> +#define UNLOCK_KEY2	0x556699aa
> +#define LOCK_KEY	0
> +
> +#define RSWRST          0x1250
> +
> +void _machine_restart(void)
> +{
> +	void __iomem *base;
> +
> +	base = pic32_get_syscfg_base();
> +
> +	/* unlock sequence */
> +	writel(LOCK_KEY, base + SYSKEY);
> +	writel(UNLOCK_KEY1, base + SYSKEY);
> +	writel(UNLOCK_KEY2, base + SYSKEY);
> +
> +	/* soft reset */
> +	writel(0x1, base + RSWRST);
> +	(void) readl(base + RSWRST);
> +
> +	while (1)
> +		;
> +}
> 

-- 
- Daniel