From: Heiko Schocher <hs@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 3/3] board: atmel: siemens: clean up PLLB code
Date: Tue, 2 Feb 2016 06:33:31 +0100 [thread overview]
Message-ID: <56B03FAB.2090401@denx.de> (raw)
In-Reply-To: <1454384133-27666-4-git-send-email-wenyou.yang@atmel.com>
Hello Wenyou,
Am 02.02.2016 um 04:35 schrieb Wenyou Yang:
> Due to introducing the new PLLB clock handle functions,
> use these functions to clean up the PLLB enable code.
>
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> Reviewed-by: Andreas Bie?mann <andreas.devel@googlemail.com>
> ---
>
> Changes in v3: None
> Changes in v2:
> - collect Reviewed-by from Andreas.
>
> board/siemens/smartweb/smartweb.c | 6 +-----
> board/siemens/taurus/taurus.c | 6 +-----
> 2 files changed, 2 insertions(+), 10 deletions(-)
Tested-by: Heiko Schocher <hs@denx.de>
bye,
Heiko
>
> diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c
> index e7ee65c..47a60a7 100644
> --- a/board/siemens/smartweb/smartweb.c
> +++ b/board/siemens/smartweb/smartweb.c
> @@ -115,12 +115,8 @@ static void smartweb_macb_hw_init(void)
>
> void at91_udp_hw_init(void)
> {
> - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
> -
> /* Enable PLLB */
> - writel(get_pllb_init(), &pmc->pllbr);
> - while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
> - ;
> + at91_pllb_clk_enable(get_pllb_init());
>
> /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
> at91_periph_clk_enable(ATMEL_ID_UDP);
> diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
> index 9374064..b0385d8 100644
> --- a/board/siemens/taurus/taurus.c
> +++ b/board/siemens/taurus/taurus.c
> @@ -289,12 +289,8 @@ void spi_cs_deactivate(struct spi_slave *slave)
>
> void at91_udp_hw_init(void)
> {
> - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
> -
> /* Enable PLLB */
> - writel(get_pllb_init(), &pmc->pllbr);
> - while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
> - ;
> + at91_pllb_clk_enable(get_pllb_init());
>
> /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
> at91_periph_clk_enable(ATMEL_ID_UDP);
>
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
prev parent reply other threads:[~2016-02-02 5:33 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-02 3:35 [U-Boot] [PATCH v3 0/3] ARM: at91: add PLLB handle functions Wenyou Yang
2016-02-02 3:35 ` [U-Boot] [PATCH v3 1/3] ARM: at91: clock: add PLLB enable/disable functions Wenyou Yang
2016-02-02 5:32 ` Heiko Schocher
2016-02-02 6:15 ` Yang, Wenyou
2016-02-02 3:35 ` [U-Boot] [PATCH v3 2/3] drivers: usb: ohci-at91: clean up the PLLB code Wenyou Yang
2016-02-02 5:33 ` Heiko Schocher
2016-02-02 3:35 ` [U-Boot] [PATCH v3 3/3] board: atmel: siemens: clean up " Wenyou Yang
2016-02-02 5:33 ` Heiko Schocher [this message]
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