[U-Boot] [PATCH 1/2] atmel_nand_ecc: update pmecc registers according to sama5d2 chip

["Andreas Bießmann" <andreas.devel@googlemail.com>]

On 24.11.2015 09:34, Josh Wu wrote:
> 1. add the pmecc register mapping for sama5d2.
> 2. add the pmecc error location register mapping for sama5d2.
> 3. add some new field that is different from old ip.
> 4. add sama5d2 pmecc ip version number.
> 
> Signed-off-by: Josh Wu <josh.wu@atmel.com>

Reviewed-by: Andreas Bie?mann <andreas.devel@googlemail.com>

> ---
> 
>  drivers/mtd/nand/atmel_nand_ecc.h | 36 ++++++++++++++++++++++++++++++++----
>  1 file changed, 32 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h
> index 79e3994..e13f385 100644
> --- a/drivers/mtd/nand/atmel_nand_ecc.h
> +++ b/drivers/mtd/nand/atmel_nand_ecc.h
> @@ -58,14 +58,23 @@ struct pmecc_regs {
>  
>  	/* 0x40 + sector_num * (0x40), Redundancy Registers */
>  	struct {
> +#ifdef CONFIG_SAMA5D2
> +		u8 ecc[56];	/* PMECC Generated Redundancy Byte Per Sector */
> +		u32 reserved1[2];
> +#else
>  		u8 ecc[44];	/* PMECC Generated Redundancy Byte Per Sector */
>  		u32 reserved1[5];
> +#endif
>  	} ecc_port[PMECC_MAX_SECTOR_NUM];
>  
>  	/* 0x240 + sector_num * (0x40) Remainder Registers */
>  	struct {
> +#ifdef CONFIG_SAMA5D2
> +		u32 rem[16];
> +#else
>  		u32 rem[12];
>  		u32 reserved2[4];
> +#endif
>  	} rem_port[PMECC_MAX_SECTOR_NUM];
>  	u32 reserved3[16];	/* 0x440-0x47C Reserved */
>  };
> @@ -76,6 +85,7 @@ struct pmecc_regs {
>  #define		PMECC_CFG_BCH_ERR8		(2 << 0)
>  #define		PMECC_CFG_BCH_ERR12		(3 << 0)
>  #define		PMECC_CFG_BCH_ERR24		(4 << 0)
> +#define		PMECC_CFG_BCH_ERR32		(5 << 0)
>  
>  #define		PMECC_CFG_SECTOR512		(0 << 4)
>  #define		PMECC_CFG_SECTOR1024		(1 << 4)
> @@ -120,19 +130,31 @@ struct pmecc_errloc_regs {
>  	u32 elimr;	/* 0x0C Error Location Interrupt Mask Register */
>  	u32 elisr;	/* 0x20 Error Location Interrupt Status Register */
>  	u32 reserved0;	/* 0x24 Reserved */
> +#ifdef CONFIG_SAMA5D2
> +	u32 sigma[33];	/* 0x28-0xA8 Error Location Sigma Registers */
> +	u32 el[32];	/* 0xAC-0x128 Error Location Registers */
> +
> +	/*
> +	 * 0x12C-0x1FC:
> +	 *   Reserved for SAMA5D2.
> +	 */
> +	u32 reserved1[53];
> +#else
>  	u32 sigma[25];	/* 0x28-0x88 Error Location Sigma Registers */
>  	u32 el[24];	/* 0x8C-0xE8 Error Location Registers */
>  	u32 reserved1[5];	/* 0xEC-0xFC Reserved */
> +#endif
>  
>  	/*
> -	 * 0x100-0x1F8:
> -	 *   Reserved for AT91SAM9X5, AT91SAM9N12.
> -	 *   HSMC registers for SAMA5D3, SAMA5D4.
> +	 * SAMA5 chip HSMC registers start here. But for 9X5 chip it is just
> +	 * reserved.
> +	 *
> +	 * Offset 0x00-0xF8:
>  	 */
>  	u32 reserved2[63];
>  
>  	/*
> -	 * 0x1FC:
> +	 * Offset 0xFC:
>  	 *   PMECC version for AT91SAM9X5, AT91SAM9N12.
>  	 *   HSMC version for SAMA5D3, SAMA5D4. Can refer as PMECC version.
>  	 */
> @@ -148,10 +170,16 @@ struct pmecc_errloc_regs {
>  #define		PMERRLOC_DISABLE		(1 << 0)
>  
>  /* For Error Location Interrupt Status Register */
> +#ifdef CONFIG_SAMA5D2
> +#define		PMERRLOC_ERR_NUM_MASK		(0x3f << 8)
> +#else
>  #define		PMERRLOC_ERR_NUM_MASK		(0x1f << 8)
> +#endif
> +
>  #define		PMERRLOC_CALC_DONE		(1 << 0)
>  
>  /* PMECC IP version */
> +#define PMECC_VERSION_SAMA5D2			0x210
>  #define PMECC_VERSION_SAMA5D4			0x113
>  #define PMECC_VERSION_SAMA5D3			0x112
>  #define PMECC_VERSION_AT91SAM9N12		0x102
>