From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] Newbie SPL question for socfpga_sockit
Date: Thu, 03 Mar 2016 23:09:17 +0100 [thread overview]
Message-ID: <56D8B60D.8020206@denx.de> (raw)
In-Reply-To: <CAMcKmiFAzfe+b9ruukYnkq7GhDCojOgONCSQB0THTwPaaacWuw@mail.gmail.com>
On 03/03/2016 11:00 PM, George Broz wrote:
> On 3 March 2016 at 06:51, Marek Vasut <marex@denx.de> wrote:
>> On 03/03/2016 03:48 PM, Dinh Nguyen wrote:
>>>
>>>
>>> On 03/02/2016 05:24 PM, Marek Vasut wrote:
>>>>
>>>> Well, that's our usual USB/QSPI cache issue that's tormenting your soul.
>>>> CCing Chin ;-)
>>>>
>>>> Does the issue by any chance magically disappear if you apply this patch:
>>>>
>>>> diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
>>>> index 026e7ef..06802c6 100644
>>>> --- a/arch/arm/include/asm/system.h
>>>> +++ b/arch/arm/include/asm/system.h
>>>> @@ -274,7 +274,7 @@ static inline void set_dacr(unsigned int val)
>>>>
>>>> /* options available for data cache on each page */
>>>> enum dcache_option {
>>>> - DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
>>>> + DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
>>>> TTB_SECT_XN_MASK | TTB_SECT,
>>>> DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
>>>> DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
>>>> DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
>>>>
>
> The 2016.01 code I'm using already includes this patch. If I try
> reading a USB stick with dcache on or off
> I get the same result:
>
> => dcache off
> => usb reset
> resetting USB...
> USB0: Core Release: 2.93a
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> dwc_otg_core_host_init: Timeout!
> scanning bus 0 for devices... 1 USB Device(s) found
> => usb tree
> USB device tree:
> 1 Hub (480 Mb/s, 0mA)
> U-Boot Root Hub
This more likely means that either clock or reset bits are not
configured correctly OR you're using the wrong controller. Since
you're mixing old U-Boot SPL with new U-Boot, there can be some
discrepancy and I have no idea how to help you with that :(
Best regards,
Marek Vasut
next prev parent reply other threads:[~2016-03-03 22:09 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-17 21:54 [U-Boot] Newbie SPL question for socfpga_sockit George Broz
2016-02-18 2:45 ` Phil Reid
2016-03-02 2:40 ` George Broz
2016-03-02 3:49 ` Phil Reid
2016-03-03 6:49 ` George Broz
2016-03-03 7:11 ` Phil Reid
2016-03-03 14:57 ` George Broz
2016-03-09 1:42 ` Phil Reid
2016-03-09 10:55 ` Marek Vasut
2016-03-09 16:06 ` George Broz
2016-03-16 1:29 ` George Broz
2016-03-16 16:17 ` George Broz
2016-03-17 1:35 ` Marek Vasut
2016-03-18 18:59 ` George Broz
2016-03-18 19:32 ` Marek Vasut
2016-03-18 21:22 ` George Broz
2016-03-19 11:10 ` Phil Reid
2016-03-20 16:44 ` Marek Vasut
2016-03-20 16:49 ` Marek Vasut
2016-03-29 1:56 ` George Broz
2016-03-29 17:46 ` Marek Vasut
2016-03-20 15:55 ` Dinh Nguyen
2016-03-20 16:42 ` Marek Vasut
2016-03-22 17:06 ` Dinh Nguyen
2016-03-26 20:52 ` Marek Vasut
2016-04-05 8:33 ` Phil Reid
2016-04-05 22:03 ` Marek Vasut
2016-04-06 0:31 ` George Broz
2016-04-06 0:45 ` Marek Vasut
2016-04-06 1:17 ` George Broz
2016-04-06 10:43 ` Marek Vasut
2016-04-07 1:42 ` George Broz
2016-04-07 2:05 ` Marek Vasut
2016-04-07 13:14 ` George Broz
2016-04-07 20:39 ` Marek Vasut
2016-04-07 23:31 ` George Broz
2016-04-07 23:36 ` Marek Vasut
2016-04-07 23:51 ` George Broz
2016-04-08 5:16 ` Stefan Roese
2016-04-08 12:36 ` Marek Vasut
2016-04-08 22:40 ` George Broz
2016-04-10 17:47 ` Marek Vasut
2016-04-11 2:03 ` George Broz
2016-04-11 14:02 ` Marek Vasut
2016-04-12 15:53 ` Dinh Nguyen
2016-04-12 16:00 ` Marek Vasut
2016-04-12 16:08 ` Dinh Nguyen
2016-04-12 16:11 ` Marek Vasut
2016-04-13 9:25 ` Chin Liang See
2016-04-12 16:09 ` Stefan Roese
2016-04-13 11:09 ` Marek Vasut
2016-04-06 7:00 ` Phil Reid
2016-04-06 11:51 ` Marek Vasut
2016-04-06 15:04 ` Phil Reid
2016-04-06 20:38 ` Marek Vasut
2016-03-29 1:44 ` George Broz
2016-03-29 17:45 ` Marek Vasut
2016-03-03 21:16 ` George Broz
2016-03-02 22:54 ` Dinh Nguyen
2016-03-02 23:04 ` Marek Vasut
2016-03-02 23:08 ` Dinh Nguyen
2016-03-02 23:24 ` Marek Vasut
2016-03-03 14:48 ` Dinh Nguyen
2016-03-03 14:51 ` Marek Vasut
2016-03-03 22:00 ` George Broz
2016-03-03 22:09 ` Marek Vasut [this message]
[not found] ` <CAMcKmiG8OMmbZ262n8gL7eM=WAgaakaZ5rWzCC1vYu7yzGBYAA@mail.gmail.com>
[not found] ` <56D8BDD7.8070604@denx.de>
[not found] ` <CAMcKmiGrZ94sZKY85Y3aC1_fwgV8oJeAJ0O71bY=gMxUGBp=FQ@mail.gmail.com>
[not found] ` <56D8C3A0.9020204@denx.de>
2016-03-03 23:46 ` George Broz
2016-03-04 16:52 ` Dinh Nguyen
2016-03-04 16:06 ` Dinh Nguyen
2016-03-04 19:03 ` Marek Vasut
2016-03-21 14:05 ` Chin Liang See
2016-03-21 15:45 ` Chin Liang See
2016-03-23 15:00 ` Chin Liang See
2016-03-23 15:37 ` [U-Boot] SoCFPGA cache / S-bit problem - was " Stefan Roese
2016-04-06 16:35 ` Dinh Nguyen
2016-04-06 16:46 ` Marek Vasut
2016-04-06 16:51 ` Dinh Nguyen
2016-03-03 6:55 ` [U-Boot] " George Broz
2016-03-03 9:48 ` Marek Vasut
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