From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Thu, 03 Mar 2016 23:09:17 +0100 Subject: [U-Boot] Newbie SPL question for socfpga_sockit In-Reply-To: References: <56C53059.4020505@electromag.com.au> <56D76F12.6060006@opensource.altera.com> <56D77289.6080808@opensource.altera.com> <56D77646.7060804@denx.de> <56D84EB0.7060104@opensource.altera.com> <56D84F69.9030007@denx.de> Message-ID: <56D8B60D.8020206@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 03/03/2016 11:00 PM, George Broz wrote: > On 3 March 2016 at 06:51, Marek Vasut wrote: >> On 03/03/2016 03:48 PM, Dinh Nguyen wrote: >>> >>> >>> On 03/02/2016 05:24 PM, Marek Vasut wrote: >>>> >>>> Well, that's our usual USB/QSPI cache issue that's tormenting your soul. >>>> CCing Chin ;-) >>>> >>>> Does the issue by any chance magically disappear if you apply this patch: >>>> >>>> diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h >>>> index 026e7ef..06802c6 100644 >>>> --- a/arch/arm/include/asm/system.h >>>> +++ b/arch/arm/include/asm/system.h >>>> @@ -274,7 +274,7 @@ static inline void set_dacr(unsigned int val) >>>> >>>> /* options available for data cache on each page */ >>>> enum dcache_option { >>>> - DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, >>>> + DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) | >>>> TTB_SECT_XN_MASK | TTB_SECT, >>>> DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, >>>> DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, >>>> DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), >>>> > > The 2016.01 code I'm using already includes this patch. If I try > reading a USB stick with dcache on or off > I get the same result: > > => dcache off > => usb reset > resetting USB... > USB0: Core Release: 2.93a > dwc_otg_core_host_init: Timeout! > dwc_otg_core_host_init: Timeout! > dwc_otg_core_host_init: Timeout! > dwc_otg_core_host_init: Timeout! > dwc_otg_core_host_init: Timeout! > dwc_otg_core_host_init: Timeout! > dwc_otg_core_host_init: Timeout! > dwc_otg_core_host_init: Timeout! > dwc_otg_core_host_init: Timeout! > dwc_otg_core_host_init: Timeout! > dwc_otg_core_host_init: Timeout! > dwc_otg_core_host_init: Timeout! > dwc_otg_core_host_init: Timeout! > dwc_otg_core_host_init: Timeout! > dwc_otg_core_host_init: Timeout! > scanning bus 0 for devices... 1 USB Device(s) found > => usb tree > USB device tree: > 1 Hub (480 Mb/s, 0mA) > U-Boot Root Hub This more likely means that either clock or reset bits are not configured correctly OR you're using the wrong controller. Since you're mixing old U-Boot SPL with new U-Boot, there can be some discrepancy and I have no idea how to help you with that :( Best regards, Marek Vasut