[U-Boot] Newbie SPL question for socfpga_sockit

George Broz
2016-03-03T21:16:36Z

On 2 March 2016 at 23:11, Phil Reid <preid@electromag.com.au> wrote:
> On 3/03/2016 2:49 PM, George Broz wrote:
>>
>> On 1 March 2016 at 19:49, Phil Reid <preid@electromag.com.au> wrote:
>>>
>>> On 2/03/2016 10:40 AM, George Broz wrote:
>>>
>>>> Sorry for the delayed response - got called away, but am back to this
>>>> now. I patched
>>>> socfpga_common.h and re-built the project. I picked up
>>>> spl/u-boot-spl-dtb.sfp and
>>>> u-boot-dtb.img and transferred them to the SD card with:
>>>>
>>>> dd if=u-boot-spl-dtb.sfp of=/dev/sdf3 bs=64k seek=0
>>>> dd if=u-boot-dtb.img of=/dev/sdf3 bs=64k seek=4
>>>>
>>>> Tried this with both the original DT set (socfpga.dtsi,
>>>> socfpga_cyclone.dtsi,
>>>> socfpga_cyclone5_sockit.dts) that came with the u-boot v2016.01 download
>>>> and
>>>> also an Altera-patched DT set that I've used to boot into Linux numerous
>>>> times.
>>>>
>>>> When I start up the board I get:
>>>>
>>>> U-Boot SPL 2016.01 (Mar 01 2016 - 17:28:14)
>>>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>>>> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
>>>> drivers/ddr/altera/sequencer.c: Calibration complete
>>>> SDRAM calibration failed.
>>>> ### ERROR ### Please RESET the board ###
>>>>
>>>> I'm not a Quartus user, so I haven't done anything with the
>>>> qts-filter.sh script you
>>>> mentioned. Do I need to? I don't have any custom FPGA logic - it's
>>>> just the Terasic
>>>> board out of the box.
>>>>
>>>> Thanks for any help!
>>>>
>>>
>>> Even without the custom FPGA logic the files generated from qts-filter.sh
>>> need to match your board.
>>> Sets up PLL and SDRAM parameters.
>>> I'm not familiar with the Terasic dev board ( I do have the altera
>>> devkit,
>>> but haven't used it for awhile).
>>> I'd hope the files in the git repo are correct for your board.
>>> Without the corresponding qsys project it's hard to be sure.
>>>
>> Hi Phil,
>>
>> So as my next attempt, there was a Quartus/Qsys example that came
>> with the Terasic board (specific to my Rev. of the board).
>>
>> * I took the contents of the 'handoff folder', .sof, and .sopcinfo file.
>> * launched an "Embedded Command Shell" from EDS 15.0 and then the BSP
>> editor GUI
>> * pointed the BSP editor to the "handoff folder", and hit "Generate"
>> to produce iocsr, pinmux, pll, etc. files
>> * applied qts-filter.sh to these files, the output of which I then
>> dropped into the u-boot source @ ../board/terasic/sockit/qts
>> * rebuilt uboot spl & image, but got a similar result:

> What does a diff of the new files show compared to the ones in uboot.
> I'm using the Quartus 15.0 tool chain at the moment.
> Turning on debugging in drivers/ddr/altera/sequencer.c may help.
>
>
> --
> Regards
> Phil Reid
>

If I build the SPL using in the embedded_command_shell environment:

~/altera/15/embedded/embedded_command_shell.sh
cd ~/<to-folder-generated-by-BSP editor>/software/spl_bsp
make

I get a working preloader-mkpimage.bin that seems to work with the
u-boot.img generated from the 2016.01 release:

U-Boot SPL 2013.01.01 (Mar 03 2016 - 08:10:01)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 925 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 370000 KHz
RESET: WARM
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 1024 MiB
ALTERA DWMMC: 0

U-Boot 2016.01 (Mar 03 2016 - 13:02:56 -0800)

CPU: Altera SoCFPGA Platform
FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT: SD/MMC Internal Transceiver (3.0V)
Watchdog enabled
I2C: ready
DRAM: 1 GiB
MMC: dwmmc0 at ff704000: 0
In: serial
Out: serial
Err: serial
Model: Terasic SoCkit
Net:
Error: ethernet at ff702000 address not set.
No ethernet found.
Hit any key to stop autoboot: 0

That would seem to indicate at least my quartus/qsys project and the files it
generates are valid and that something is amiss with the terasic board
support code?

BTW - if I set DLEVEL=1 in sequencer.c with the 2016.01-generated SPL I get:

U-Boot SPL 2016.01 (Mar 03 2016 - 11:24:11)
scc_mgr_initialize:281: Clearing SCC RFILE index 0
scc_mgr_initialize:281: Clearing SCC RFILE index 1
scc_mgr_initialize:281: Clearing SCC RFILE index 2
scc_mgr_initialize:281: Clearing SCC RFILE index 3
scc_mgr_initialize:281: Clearing SCC RFILE index 4
scc_mgr_initialize:281: Clearing SCC RFILE index 5
scc_mgr_initialize:281: Clearing SCC RFILE index 6
scc_mgr_initialize:281: Clearing SCC RFILE index 7
scc_mgr_initialize:281: Clearing SCC RFILE index 8
scc_mgr_initialize:281: Clearing SCC RFILE index 9
scc_mgr_initialize:281: Clearing SCC RFILE index 10
scc_mgr_initialize:281: Clearing SCC RFILE index 11
scc_mgr_initialize:281: Clearing SCC RFILE index 12
scc_mgr_initialize:281: Clearing SCC RFILE index 13
scc_mgr_initialize:281: Clearing SCC RFILE index 14
scc_mgr_initialize:281: Clearing SCC RFILE index 15

If that's of use to anyone...

Thanks,
--George