From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Zhong Date: Tue, 8 Mar 2016 08:48:18 +0800 Subject: [U-Boot] [PATCH v2] rockchip: rk3288: correct sdram setting In-Reply-To: References: <1457333473-19860-1-git-send-email-zyw@rock-chips.com> Message-ID: <56DE2152.909@rock-chips.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 2016?03?08? 02:30, Simon Glass wrote: > Hi Chris, > > On 6 March 2016 at 23:51, Chris Zhong wrote: >> The DMC driver in v3.14 kernel[0] get the ddr setting from PMU_SYS_REG2, >> and it expects uboot to store the value using a same protocol. But now >> the ddr setting value is different with DMC, so if you enable the DMC, >> system would crash in kernel. Correct the sdram setting here, according >> to the requirements of kernel. >> >> [0] >> https://chromium.googlesource.com/chromiumos/third_party/kernel/+/ >> chromeos-3.14/drivers/clk/rockchip/clk-rk3288-dmc.c >> >> Signed-off-by: Chris Zhong >> --- >> >> Changes in v2: >> Modified into a more readable code style(Simon Glass) >> >> arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 14 +++++++------- >> 1 file changed, 7 insertions(+), 7 deletions(-) > Acked-by: Simon Glass > > Longer term, might it be possible to write this info into the device > tree and pass it to Linux that way? Yes, agree, that would be better. At least not need so many complicated calculations. > >> diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c >> index e9e2211..17daeca 100644 >> --- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c >> +++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c >> @@ -561,14 +561,14 @@ static void dram_all_config(const struct dram_info *dram, >> &sdram_params->ch[chan]; >> >> sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); >> - sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan); >> + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); >> sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); >> sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); >> - sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0; >> + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); >> sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); >> sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); >> - sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan); >> - sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan); >> + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); >> + sys_reg |= (2 >>info->dbw) << SYS_REG_DBW_SHIFT(chan); >> >> dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); >> } >> @@ -720,13 +720,13 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu) >> rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & >> SYS_REG_RANK_MASK); >> col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); >> - bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0; >> + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK) ; >> cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & >> SYS_REG_CS0_ROW_MASK); >> cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & >> SYS_REG_CS1_ROW_MASK); >> - bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) & >> - SYS_REG_BW_MASK; >> + bw = (2 >> (sys_reg >> SYS_REG_BW_SHIFT(ch)) & >> + SYS_REG_BW_MASK); >> row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & >> SYS_REG_ROW_3_4_MASK; >> >> -- >> 1.9.1 >> > Regards, > Simon > > >