[U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

[Stefano Babic <sbabic@denx.de>]

Hi Peng, Ye,

On 09/03/2016 09:13, Peng Fan wrote:
> From: Ye Li <ye.li@nxp.com>
> 
> Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register
> the bit[17] for mmdc_ch0 is reserved and its proper state should be 1.
> When clear this bit, the periph_clk_sel cannot be set and that
> CDHIPR[periph_clk_sel_busy] handshake never clears.
> 
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <van.freenix@gmail.com>
> ---
>  arch/arm/cpu/armv7/mx6/soc.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index 91a3deb..bdd41b0 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void)
>  	reg = readl(&mxc_ccm->ccdr);
>  
>  	/* Clear MMDC channel mask */
> -	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
> +	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL))
> +		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
> +	else
> +		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
>  	writel(reg, &mxc_ccm->ccdr);
>  }
>  

Acked-by: Stefano Babic <sbabic@denx.de>

This is a fix, and my question to you both: is it enough to merge it
after 2016.03 ? I have not read about big issues due to periph_clk_sel,
and maybe we can postponed it (or I merge directly into -next as several
of you have already proposed).

Best regards,
Stefano Babic



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