From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] Newbie SPL question for socfpga_sockit
Date: Wed, 09 Mar 2016 11:55:06 +0100 [thread overview]
Message-ID: <56E0010A.6010202@denx.de> (raw)
In-Reply-To: <56DF7F80.4060602@electromag.com.au>
On 03/09/2016 02:42 AM, Phil Reid wrote:
> G'day George,
>
> On 3/03/2016 10:57 PM, George Broz wrote:
>> On 2 March 2016 at 23:11, Phil Reid <preid@electromag.com.au> wrote:
>>> On 3/03/2016 2:49 PM, George Broz wrote:
>>>>
>>>> On 1 March 2016 at 19:49, Phil Reid <preid@electromag.com.au> wrote:
>>>>>
>>>>> On 2/03/2016 10:40 AM, George Broz wrote:
>>>>>
>>>>>> Sorry for the delayed response - got called away, but am back to this
>>>>>> now. I patched
>>>>>> socfpga_common.h and re-built the project. I picked up
>>>>>> spl/u-boot-spl-dtb.sfp and
>>>>>> u-boot-dtb.img and transferred them to the SD card with:
>>>>>>
>>>>>> dd if=u-boot-spl-dtb.sfp of=/dev/sdf3 bs=64k seek=0
>>>>>> dd if=u-boot-dtb.img of=/dev/sdf3 bs=64k seek=4
>>>>>>
>>>>>> Tried this with both the original DT set (socfpga.dtsi,
>>>>>> socfpga_cyclone.dtsi,
>>>>>> socfpga_cyclone5_sockit.dts) that came with the u-boot v2016.01
>>>>>> download
>>>>>> and
>>>>>> also an Altera-patched DT set that I've used to boot into Linux
>>>>>> numerous
>>>>>> times.
>>>>>>
>>>>>> When I start up the board I get:
>>>>>>
>>>>>> U-Boot SPL 2016.01 (Mar 01 2016 - 17:28:14)
>>>>>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>>>>>> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
>>>>>> drivers/ddr/altera/sequencer.c: Calibration complete
>>>>>> SDRAM calibration failed.
>>>>>> ### ERROR ### Please RESET the board ###
>>>>>>
>>>>>> I'm not a Quartus user, so I haven't done anything with the
>>>>>> qts-filter.sh script you
>>>>>> mentioned. Do I need to? I don't have any custom FPGA logic - it's
>>>>>> just the Terasic
>>>>>> board out of the box.
>>>>>>
>>>>>> Thanks for any help!
>>>>>>
>>>>>
>>>>> Even without the custom FPGA logic the files generated from
>>>>> qts-filter.sh
>>>>> need to match your board.
>>>>> Sets up PLL and SDRAM parameters.
>>>>> I'm not familiar with the Terasic dev board ( I do have the altera
>>>>> devkit,
>>>>> but haven't used it for awhile).
>>>>> I'd hope the files in the git repo are correct for your board.
>>>>> Without the corresponding qsys project it's hard to be sure.
>>>>>
>>>> Hi Phil,
>>>>
>>>> So as my next attempt, there was a Quartus/Qsys example that came
>>>> with the Terasic board (specific to my Rev. of the board).
>>>>
>>>> * I took the contents of the 'handoff folder', .sof, and .sopcinfo
>>>> file.
>>>> * launched an "Embedded Command Shell" from EDS 15.0 and then the BSP
>>>> editor GUI
>>>> * pointed the BSP editor to the "handoff folder", and hit "Generate"
>>>> to produce iocsr, pinmux, pll, etc. files
>>>> * applied qts-filter.sh to these files, the output of which I then
>>>> dropped into the u-boot source @ ../board/terasic/sockit/qts
>>>> * rebuilt uboot spl & image, but got a similar result:
>>>>
>>>> U-Boot SPL 2016.01 (Mar 02 2016 - 22:13:31)
>>>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>>>> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED
>>>> drivers/ddr/altera/sequencer.c: Calibration complete
>>>> SDRAM calibration failed.
>>>> ### ERROR ### Please RESET the board ###
>>>>
>>>> Except now it repeats four times, whereas before it only printed out
>>>> once.
>>>>
>>>> It that essentially the correct procedure? Is it now a matter of
>>>> looking through
>>>> the include files that where generated by qts-filter.sh to find a
>>>> setting that is "off"?
>>>>
>>>> (BTW - my first attempt was to use EDS 13.0, but that resulted in
>>>> several undefined macros when it
>>>> came time to compile u-boot with the qts-filter-generated code. How
>>>> does one know which tool version to use?)
>>>>
>>>
>>> What does a diff of the new files show compared to the ones in uboot.
>>
>> Here's two of them...
>>
>> ---
>> /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/sdram_config.h.orig
>>
>> +++
>> /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/sdram_config.h
>>
>>
>> @@ -33,10 +33,10 @@
>> #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
>> #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
>> #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
>> -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
>> -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12
>> -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
>> -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
>> +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
>> +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15
>> +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
>> +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
>> #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
>> #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
>> #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
>>
>> @@ -46,12 +46,12 @@
>> #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
>> #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
>> #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
>> -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
>> +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
>> #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
>> #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
>> #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
>> #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
>> -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
>> +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
>> #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
>> #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
>> #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
>>
>> @@ -147,7 +147,7 @@
>> #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
>> #define MAX_LATENCY_COUNT_WIDTH 5
>> #define READ_VALID_FIFO_SIZE 16
>> -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
>> +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
>> #define RW_MGR_MEM_ADDRESS_MIRRORING 0
>> #define RW_MGR_MEM_DATA_MASK_WIDTH 4
>> #define RW_MGR_MEM_DATA_WIDTH 32
>>
>> @@ -168,19 +168,20 @@
>>
>> #define TRESET_CNTR2_VAL 10
>> /* Sequencer ac_rom_init configuration */
>> -const u32 ac_rom_init[] = {
>> +const u32 ac_rom_init[] =
>> +{
>> 0x20700000,
>> 0x20780000,
>> 0x10080431,
>> 0x10080530,
>> 0x10090044,
>> - 0x100a0008,
>> + 0x100a0010,
>> 0x100b0000,
>> 0x10380400,
>> 0x10080449,
>> 0x100804c8,
>> 0x100a0024,
>> - 0x10090010,
>> + 0x10090008,
>> 0x100b0000,
>> 0x30780000,
>> 0x38780000,
>>
>> @@ -208,7 +209,8 @@
>> };
>>
>>
>> /* Sequencer inst_rom_init configuration */
>> -const u32 inst_rom_init[] = {
>> +const u32 inst_rom_init[] =
>> +{
>> 0x80000,
>> 0x80680,
>> 0x8180,
>>
>> ---
>> /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/pll_config.h.orig
>>
>> +++
>> /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/pll_config.h
>>
>> @@ -16,7 +16,7 @@
>> #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
>> #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
>> #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
>> -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
>> +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18
>> #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
>> #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
>> #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
>>
>>
>>> I'm using the Quartus 15.0 tool chain at the moment.
>>> Turning on debugging in drivers/ddr/altera/sequencer.c may help.
>>>
>>
>> Setting DLEVEL = 2 yields:
>>
>> U-Boot SPL 2016.01 (Mar 03 2016 - 06:28:33)
>> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration
>> find_vfifo_failing_read:1519: vfifo 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> find_vfifo_failing_read:1519: vfifo 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1864 p: ptap=4
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1877 p/d: ptap=4 dtap=7
>> end=16399
>> rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1887 found range
>> [14003,16399]
>> rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1895 calculate
>> dtaps_per_ptap for tracking
>> rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1906 backedup phase only:
>> p=3rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1919 find passing read
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1927 find failing read
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0
>> rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1948 dtaps_per_ptap=21 -
>> 8 = 13work_bgn=14003 work_end=16399 work_mid=15201
>> vfifo ptap delay 2496
>> new work_mid 225
>> new p 0, tmp_delay=0
>> new d 9, tmp_delay=225
>> find_dqs_en_phase: center
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1
>> sdr_find_window_center:1779 center: found: ptap=0 dtap=9
>> rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1
>> search_stop_check:2006 center(left): dtap=0 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=1 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=2 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=3 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=4 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=5 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=6 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=7 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=8 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=9 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=10 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=11 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=12 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=13 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=14 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=15 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (187 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=16 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (179 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=17 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (19 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=18 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (17 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=19 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (16 != 0)
>> => 1
>> search_stop_check:2006 center(left): dtap=20 => 255 == 255 &&
>> 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) =>
>> 0
>> search_stop_check:2006 center(left): dtap=21 => 255 == 255 &&?
>>
>> Will try to make sense of these today...
>>
>> Any insights welcome!
>>
>
> Any success.
>
> You've reached the limits of my knowledge.
> The diff shows that there are differences in config.
> Failure of Memory Calibration has always been my biggest fear with
> hardware design.
>
> Interesting that the 2013.01 build from the Quartus tools works.
> But the 2016.01 using the same qts generated files does not.
> Which would suggest there is something amiss in the code.
>
> Is there similar debug statements in the 2013.01 code?
There is debug(), which you can enable by adding #define DEBUG at the
beginning of drivers/ddr/altera/*.c . The other way of tracking down
this bug would be to rig the writel()/readl() calls and check what
values they use compared to the original altera code.
> I'll try and find time to build with the 2016.01 debug statements here
> and send you a log for comparison.
>
>
--
Best regards,
Marek Vasut
next prev parent reply other threads:[~2016-03-09 10:55 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-17 21:54 [U-Boot] Newbie SPL question for socfpga_sockit George Broz
2016-02-18 2:45 ` Phil Reid
2016-03-02 2:40 ` George Broz
2016-03-02 3:49 ` Phil Reid
2016-03-03 6:49 ` George Broz
2016-03-03 7:11 ` Phil Reid
2016-03-03 14:57 ` George Broz
2016-03-09 1:42 ` Phil Reid
2016-03-09 10:55 ` Marek Vasut [this message]
2016-03-09 16:06 ` George Broz
2016-03-16 1:29 ` George Broz
2016-03-16 16:17 ` George Broz
2016-03-17 1:35 ` Marek Vasut
2016-03-18 18:59 ` George Broz
2016-03-18 19:32 ` Marek Vasut
2016-03-18 21:22 ` George Broz
2016-03-19 11:10 ` Phil Reid
2016-03-20 16:44 ` Marek Vasut
2016-03-20 16:49 ` Marek Vasut
2016-03-29 1:56 ` George Broz
2016-03-29 17:46 ` Marek Vasut
2016-03-20 15:55 ` Dinh Nguyen
2016-03-20 16:42 ` Marek Vasut
2016-03-22 17:06 ` Dinh Nguyen
2016-03-26 20:52 ` Marek Vasut
2016-04-05 8:33 ` Phil Reid
2016-04-05 22:03 ` Marek Vasut
2016-04-06 0:31 ` George Broz
2016-04-06 0:45 ` Marek Vasut
2016-04-06 1:17 ` George Broz
2016-04-06 10:43 ` Marek Vasut
2016-04-07 1:42 ` George Broz
2016-04-07 2:05 ` Marek Vasut
2016-04-07 13:14 ` George Broz
2016-04-07 20:39 ` Marek Vasut
2016-04-07 23:31 ` George Broz
2016-04-07 23:36 ` Marek Vasut
2016-04-07 23:51 ` George Broz
2016-04-08 5:16 ` Stefan Roese
2016-04-08 12:36 ` Marek Vasut
2016-04-08 22:40 ` George Broz
2016-04-10 17:47 ` Marek Vasut
2016-04-11 2:03 ` George Broz
2016-04-11 14:02 ` Marek Vasut
2016-04-12 15:53 ` Dinh Nguyen
2016-04-12 16:00 ` Marek Vasut
2016-04-12 16:08 ` Dinh Nguyen
2016-04-12 16:11 ` Marek Vasut
2016-04-13 9:25 ` Chin Liang See
2016-04-12 16:09 ` Stefan Roese
2016-04-13 11:09 ` Marek Vasut
2016-04-06 7:00 ` Phil Reid
2016-04-06 11:51 ` Marek Vasut
2016-04-06 15:04 ` Phil Reid
2016-04-06 20:38 ` Marek Vasut
2016-03-29 1:44 ` George Broz
2016-03-29 17:45 ` Marek Vasut
2016-03-03 21:16 ` George Broz
2016-03-02 22:54 ` Dinh Nguyen
2016-03-02 23:04 ` Marek Vasut
2016-03-02 23:08 ` Dinh Nguyen
2016-03-02 23:24 ` Marek Vasut
2016-03-03 14:48 ` Dinh Nguyen
2016-03-03 14:51 ` Marek Vasut
2016-03-03 22:00 ` George Broz
2016-03-03 22:09 ` Marek Vasut
[not found] ` <CAMcKmiG8OMmbZ262n8gL7eM=WAgaakaZ5rWzCC1vYu7yzGBYAA@mail.gmail.com>
[not found] ` <56D8BDD7.8070604@denx.de>
[not found] ` <CAMcKmiGrZ94sZKY85Y3aC1_fwgV8oJeAJ0O71bY=gMxUGBp=FQ@mail.gmail.com>
[not found] ` <56D8C3A0.9020204@denx.de>
2016-03-03 23:46 ` George Broz
2016-03-04 16:52 ` Dinh Nguyen
2016-03-04 16:06 ` Dinh Nguyen
2016-03-04 19:03 ` Marek Vasut
2016-03-21 14:05 ` Chin Liang See
2016-03-21 15:45 ` Chin Liang See
2016-03-23 15:00 ` Chin Liang See
2016-03-23 15:37 ` [U-Boot] SoCFPGA cache / S-bit problem - was " Stefan Roese
2016-04-06 16:35 ` Dinh Nguyen
2016-04-06 16:46 ` Marek Vasut
2016-04-06 16:51 ` Dinh Nguyen
2016-03-03 6:55 ` [U-Boot] " George Broz
2016-03-03 9:48 ` Marek Vasut
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