[U-Boot] Ethernet not found on Arria 5.

[Marek Vasut <marex@denx.de>]

On 03/21/2016 09:16 AM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
> Hi,

Hi!

> I solved the Ethernet problem on our board.
> 
> The problem was in the register below:
> 
> Link: http://wl.altera.com/literature/hb/arria-v/hps.html#topic/sfo1410067853518.html
> Registers used by the EMACs. All fields are reset by a cold or warm reset.
> Module Instance	Base Address	Register Address
> sysmgr	0xFFD08000	0xFFD08060

Thanks for looking into it, try if the attached patch works for you.
Make sure you have correct phy-mode = "gmii"; DT node specified for
the GMAC you use, Arria V SoCDK surely uses phy-mode = "rgmii";

> I found that difference while comparing the dumps between OK and NOK cases.
> 
> In new U-Boot (2016) the values of 
> ctrl :: physel_0
> ctrl :: physel_1
> were always set to 
> 0x1	Select RGMII PHY interface
> 
> I changed this value to 
> 0x0	Select GMII/MII PHY interface

[...]

> But still I have this sort of question:
> Why those two registers are always assigned to RGMII PHY interface (and default value is 0x2 	Select RMII PHY interface)?
> In current code there is no way to change this value.

Most likely because noone ever had a board with PHY connected over
anything else but RGMII, so this went unnoticed.

> I changed it like this:
> 
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> old mode 100644
> new mode 100755
> index 9b43b92..295ed5a
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -23,6 +23,8 @@
> 
> @@ -97,14 +99,19 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id)
>                      SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
> 
>         /* configure to PHY interface select choosed */
> +#ifdef CONFIG_WORKAROUND
> +       setbits_le32(&sysmgr_regs->emacgrp_ctrl,
> +                    SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII << physhift);
> +#else
>         setbits_le32(&sysmgr_regs->emacgrp_ctrl,
>                     SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
> +#endif
> 
>         /* Release the EMAC controller from reset */
>         socfpga_per_reset(reset, 0);
>  }
> 
> Please evaluate my correction.
> Maybe we can assign ctrl :: physel_0 and ctrl :: physel_1 based on some switch in config?

We should parse the OF node phy-mode, which describes which mode your
PHY uses. If your DT is written correctly, then with the attached patch,
any PHY mode should work.

> Best regards,
> Denis Bakhvalov
> 


-- 
Best regards,
Marek Vasut
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