* [U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask @ 2016-03-09 8:13 Peng Fan 2016-03-09 9:47 ` Stefano Babic 0 siblings, 1 reply; 5+ messages in thread From: Peng Fan @ 2016-03-09 8:13 UTC (permalink / raw) To: u-boot From: Ye Li <ye.li@nxp.com> Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <van.freenix@gmail.com> --- arch/arm/cpu/armv7/mx6/soc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 91a3deb..bdd41b0 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void) reg = readl(&mxc_ccm->ccdr); /* Clear MMDC channel mask */ - reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL)) + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); + else + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); writel(reg, &mxc_ccm->ccdr); } -- 2.6.2 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask 2016-03-09 8:13 [U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask Peng Fan @ 2016-03-09 9:47 ` Stefano Babic 2016-03-09 9:37 ` Peng Fan 0 siblings, 1 reply; 5+ messages in thread From: Stefano Babic @ 2016-03-09 9:47 UTC (permalink / raw) To: u-boot Hi Peng, Ye, On 09/03/2016 09:13, Peng Fan wrote: > From: Ye Li <ye.li@nxp.com> > > Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register > the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. > When clear this bit, the periph_clk_sel cannot be set and that > CDHIPR[periph_clk_sel_busy] handshake never clears. > > Signed-off-by: Ye Li <ye.li@nxp.com> > Signed-off-by: Peng Fan <van.freenix@gmail.com> > --- > arch/arm/cpu/armv7/mx6/soc.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c > index 91a3deb..bdd41b0 100644 > --- a/arch/arm/cpu/armv7/mx6/soc.c > +++ b/arch/arm/cpu/armv7/mx6/soc.c > @@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void) > reg = readl(&mxc_ccm->ccdr); > > /* Clear MMDC channel mask */ > - reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); > + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL)) > + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); > + else > + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); > writel(reg, &mxc_ccm->ccdr); > } > Acked-by: Stefano Babic <sbabic@denx.de> This is a fix, and my question to you both: is it enough to merge it after 2016.03 ? I have not read about big issues due to periph_clk_sel, and maybe we can postponed it (or I merge directly into -next as several of you have already proposed). Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask 2016-03-09 9:47 ` Stefano Babic @ 2016-03-09 9:37 ` Peng Fan 2016-03-25 9:14 ` Peng Fan 0 siblings, 1 reply; 5+ messages in thread From: Peng Fan @ 2016-03-09 9:37 UTC (permalink / raw) To: u-boot Hi Stefano, On Wed, Mar 09, 2016 at 10:47:38AM +0100, Stefano Babic wrote: >Hi Peng, Ye, > >On 09/03/2016 09:13, Peng Fan wrote: >> From: Ye Li <ye.li@nxp.com> >> >> Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register >> the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. >> When clear this bit, the periph_clk_sel cannot be set and that >> CDHIPR[periph_clk_sel_busy] handshake never clears. >> >> Signed-off-by: Ye Li <ye.li@nxp.com> >> Signed-off-by: Peng Fan <van.freenix@gmail.com> >> --- >> arch/arm/cpu/armv7/mx6/soc.c | 5 ++++- >> 1 file changed, 4 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c >> index 91a3deb..bdd41b0 100644 >> --- a/arch/arm/cpu/armv7/mx6/soc.c >> +++ b/arch/arm/cpu/armv7/mx6/soc.c >> @@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void) >> reg = readl(&mxc_ccm->ccdr); >> >> /* Clear MMDC channel mask */ >> - reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); >> + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL)) >> + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); >> + else >> + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); >> writel(reg, &mxc_ccm->ccdr); >> } >> > >Acked-by: Stefano Babic <sbabic@denx.de> > >This is a fix, and my question to you both: is it enough to merge it >after 2016.03 ? I have not read about big issues due to periph_clk_sel, >and maybe we can postponed it (or I merge directly into -next as several >of you have already proposed). Yeah. It's okay to merge after 2016.03. Regards, Peng. > >Best regards, >Stefano Babic > > > >-- >===================================================================== >DENX Software Engineering GmbH, Managing Director: Wolfgang Denk >HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany >Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de >===================================================================== ^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask 2016-03-09 9:37 ` Peng Fan @ 2016-03-25 9:14 ` Peng Fan 2016-03-25 9:31 ` Stefano Babic 0 siblings, 1 reply; 5+ messages in thread From: Peng Fan @ 2016-03-25 9:14 UTC (permalink / raw) To: u-boot Hi Stefano, On Wed, Mar 09, 2016 at 05:37:28PM +0800, Peng Fan wrote: >Hi Stefano, > >On Wed, Mar 09, 2016 at 10:47:38AM +0100, Stefano Babic wrote: >>Hi Peng, Ye, >> >>On 09/03/2016 09:13, Peng Fan wrote: >>> From: Ye Li <ye.li@nxp.com> >>> >>> Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register >>> the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. >>> When clear this bit, the periph_clk_sel cannot be set and that >>> CDHIPR[periph_clk_sel_busy] handshake never clears. >>> >>> Signed-off-by: Ye Li <ye.li@nxp.com> >>> Signed-off-by: Peng Fan <van.freenix@gmail.com> >>> --- >>> arch/arm/cpu/armv7/mx6/soc.c | 5 ++++- >>> 1 file changed, 4 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c >>> index 91a3deb..bdd41b0 100644 >>> --- a/arch/arm/cpu/armv7/mx6/soc.c >>> +++ b/arch/arm/cpu/armv7/mx6/soc.c >>> @@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void) >>> reg = readl(&mxc_ccm->ccdr); >>> >>> /* Clear MMDC channel mask */ >>> - reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); >>> + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL)) >>> + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); >>> + else >>> + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); >>> writel(reg, &mxc_ccm->ccdr); >>> } >>> >> >>Acked-by: Stefano Babic <sbabic@denx.de> >> >>This is a fix, and my question to you both: is it enough to merge it >>after 2016.03 ? I have not read about big issues due to periph_clk_sel, >>and maybe we can postponed it (or I merge directly into -next as several >>of you have already proposed). > >Yeah. It's okay to merge after 2016.03. Will you pick up this patch? Regards, Peng. > >Regards, >Peng. > >> >>Best regards, >>Stefano Babic >> >> >> >>-- >>===================================================================== >>DENX Software Engineering GmbH, Managing Director: Wolfgang Denk >>HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany >>Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de >>===================================================================== ^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask 2016-03-25 9:14 ` Peng Fan @ 2016-03-25 9:31 ` Stefano Babic 0 siblings, 0 replies; 5+ messages in thread From: Stefano Babic @ 2016-03-25 9:31 UTC (permalink / raw) To: u-boot On 25/03/2016 10:14, Peng Fan wrote: > Hi Stefano, > > On Wed, Mar 09, 2016 at 05:37:28PM +0800, Peng Fan wrote: >> Hi Stefano, >> >> On Wed, Mar 09, 2016 at 10:47:38AM +0100, Stefano Babic wrote: >>> Hi Peng, Ye, >>> >>> On 09/03/2016 09:13, Peng Fan wrote: >>>> From: Ye Li <ye.li@nxp.com> >>>> >>>> Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register >>>> the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. >>>> When clear this bit, the periph_clk_sel cannot be set and that >>>> CDHIPR[periph_clk_sel_busy] handshake never clears. >>>> >>>> Signed-off-by: Ye Li <ye.li@nxp.com> >>>> Signed-off-by: Peng Fan <van.freenix@gmail.com> >>>> --- >>>> arch/arm/cpu/armv7/mx6/soc.c | 5 ++++- >>>> 1 file changed, 4 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c >>>> index 91a3deb..bdd41b0 100644 >>>> --- a/arch/arm/cpu/armv7/mx6/soc.c >>>> +++ b/arch/arm/cpu/armv7/mx6/soc.c >>>> @@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void) >>>> reg = readl(&mxc_ccm->ccdr); >>>> >>>> /* Clear MMDC channel mask */ >>>> - reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); >>>> + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL)) >>>> + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); >>>> + else >>>> + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); >>>> writel(reg, &mxc_ccm->ccdr); >>>> } >>>> >>> >>> Acked-by: Stefano Babic <sbabic@denx.de> >>> >>> This is a fix, and my question to you both: is it enough to merge it >>> after 2016.03 ? I have not read about big issues due to periph_clk_sel, >>> and maybe we can postponed it (or I merge directly into -next as several >>> of you have already proposed). >> >> Yeah. It's okay to merge after 2016.03. I do it Stefano > > Will you pick up this patch? > > Regards, > Peng. > >> >> Regards, >> Peng. >> >>> >>> Best regards, >>> Stefano Babic >>> >>> >>> >>> -- >>> ===================================================================== >>> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk >>> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany >>> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de >>> ===================================================================== -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-03-25 9:31 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-03-09 8:13 [U-Boot] [PATCH] imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask Peng Fan 2016-03-09 9:47 ` Stefano Babic 2016-03-09 9:37 ` Peng Fan 2016-03-25 9:14 ` Peng Fan 2016-03-25 9:31 ` Stefano Babic
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox