[U-Boot] [PATCH RFC 07/17] sunxi: clk: Fix USB PHY clock macros for A83T

Chen-Yu Tsai
2016-03-29T16:26:52Z

The A83T has 3 PHYs, the last one being HSIC, which has 2 clocks.
Also there is only 1 OHCI.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
index 5f93d7f..5e1346e 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
@@ -224,14 +224,14 @@ struct sunxi_ccm_reg {

#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
-#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+#define CCM_USB_CTRL_HSIC_RST (0x1 << 2)
/* There is no global phy clk gate on sun6i, define as 0 */
#define CCM_USB_CTRL_PHYGATE 0
#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8)
#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
-#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
+#define CCM_USB_CTRL_HSIC_CLK (0x1 << 10)
+#define CCM_USB_CTRL_12M_CLK (0x1 << 11)
#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
-#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)

#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
--
2.7.0