From mboxrd@z Thu Jan  1 00:00:00 1970
From: Alexander Graf <agraf@suse.de>
Date: Mon, 4 Apr 2016 09:38:05 +0200
Subject: [U-Boot] Unaligned flush_dcache_range in axs101.c
Message-ID: <570219DD.4020007@suse.de>
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To: u-boot@lists.denx.de

Hi Alexey,

Marek just pointed out to me the fact that flush_dcache_range on arm
expects cache line aligned arguments. However, it seems like in axs101.c
we have an unaligned cache flush:

  flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));

Could you please verify whether this is correct and if not just send a
quick patch to fix it?


Thanks!

Alex