From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Tue, 5 Apr 2016 09:56:37 -0700 Subject: [U-Boot] [PATCH] arm: sleep: Get the entry point of kernel from SPARE4 register In-Reply-To: <1459850484-28082-1-git-send-email-b18965@freescale.com> References: <1459850484-28082-1-git-send-email-b18965@freescale.com> Message-ID: <5703EE45.2040202@nxp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 04/05/2016 03:10 AM, Alison Wang wrote: > For LS1021A Secure Boot, SPARE2 register is used and modified by the > IBR. To avoid the conflict, SPARE4 is used instead of SPARE2 to store > the entry point of kernel. This patch is to get the entry point of > kernel from SPARE4 instead of SPARE2. > > Signed-off-by: Alison Wang > --- > board/freescale/common/arm_sleep.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c > index 71ed15e..6d967f0 100644 > --- a/board/freescale/common/arm_sleep.c > +++ b/board/freescale/common/arm_sleep.c > @@ -88,7 +88,7 @@ int fsl_dp_resume(void) > dp_resume_prepare(); > > /* Get the entry address and jump to kernel */ > - start_addr = in_le32(&scfg->sparecr[1]); > + start_addr = in_le32(&scfg->sparecr[3]); > debug("Entry address is 0x%08x\n", start_addr); > kernel_resume = (void (*)(void))start_addr; > secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0); > Alison, Does this change need to be in sync with Kernel change? York