[U-Boot] Newbie SPL question for socfpga_sockit

[Marek Vasut <marex@denx.de>]

On 04/06/2016 05:04 PM, Phil Reid wrote:
> On 6/04/2016 7:51 PM, Marek Vasut wrote:
>> On 04/06/2016 09:00 AM, Phil Reid wrote:
>>> On 6/04/2016 6:03 AM, Marek Vasut wrote:
>>>> On 04/05/2016 10:33 AM, Phil Reid wrote:
>>>>> On 27/03/2016 4:52 AM, Marek Vasut wrote:
>>>>>> On 03/22/2016 06:06 PM, Dinh Nguyen wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 03/20/2016 11:42 AM, Marek Vasut wrote:
>>>>>>>>>
>>>>>>>>> Sorry, I know that doesn't help. So let's walk through my
>>>>>>>>> workflow.
>>>>>>>>> I am
>>>>>>>>> not using any Altera tools when I build.
>>>>>>>>>
>>>>>>>>> $make socfpga_de0_nano_soc_defconfig
>>>>>>>>> $make u-boot-with-spl.sfp
>>>>>>>>> $dd if=u-boot-with-spl.sfp of=/dev/sdb3
>>>>>>>>>
>>>>>>>>> My gcc is: arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.7.3-12ubuntu1)
>>>>>>>>> 4.7.3
>>>>>>>>>
>>>>>>>>> Has the board ever worked for you at all? Can you try this image:
>>>>>>>>>
>>>>>>>>> https://rocketboards.org/foswiki/view/Documentation/AtlasSoCSdCardImage
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Dinh
>>>>>>>>
>>>>>>>> I just ported U-Boot to another customer board. I noticed QSPI has
>>>>>>>> problems and USB can be flaky. That's the standard cache issue we
>>>>>>>> have, disabling dcache fixed that.
>>>>>>>>
>>>>>>>> I am starting to wonder whether we're hitting some corner case
>>>>>>>> here.
>>>>>>>> Maybe we should eventually try and trace all the register reads and
>>>>>>>> writes generated by the DDR calibration code both in old and new
>>>>>>>> SPL
>>>>>>>> and make a diff to see if something really did change.
>>>>>>>>
>>>>>>>> Dinh, can you share the marking on the SoC and the DRAMs on your
>>>>>>>> board?
>>>>>>>>
>>>>>>>
>>>>>>> My SoC is:
>>>>>>>
>>>>>>> 5CSEMA4U23C6N
>>>>>>> CACAU1525A
>>>>>>>
>>>>>>> DRAMs are:
>>>>>>>
>>>>>>> ISSI 1510
>>>>>>> IS43TR16256A
>>>>>>> 15HBL K080
>>>>>>> P4482100QER2 TWN
>>>>>>
>>>>>> Thanks, that's indeed rev. C . About time I bang my head against the
>>>>>> desk because this is creepy.
>>>>>>
>>>>>>
>>>>> FYI
>>>>>
>>>>> I've just spend some time trying to update the spl / uboot / kernel &
>>>>> rootfs image on our
>>>>> Altera socdk to use for some software testing / development.
>>>>> Unfortunately it fails in the mem calibration process with the latest
>>>>> uboot most of the time.
>>>>> And when it does boot somtimes fails loading uboot fomr the mmc.
>>>>
>>>> Try this u-boot-socfpga/ddr branch [1] , see if it works for you.
>>>>
>>>> [1]
>>>> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/ddr
>>>>
>>>>
>>>>
>>>
>>> Spent a bit of time on it and things are very weird. So far no luck
>>> booting with the ddr branch.
>>> I got the memory calibration to pass but then had problems with loading
>>> uboot. Using the mmc.
>>> Say no device found for the mmc. error -19.
>>
>> Which board is this ? How wide is the MMC data bus ?
>>
>>> When I try to add some extra debug in things fall over.
>>> Sometimes just hangs in the Memory cal (and not changing anything
>>> there).
>>> Then sometimes I get missing DTB.
>>> I found the uboot-with-spl.sfp file generated by the latest uboot tree
>>> and tried burning that with
>>> same results.
>>>
>>> Reverted back to the image available on rocketboards and wrote that to
>>> the card.
>>> Thinking something strange with the card (thou I tried several) and that
>>> works fine.
>>> Sourced from
>>> https://rocketboards.org/foswiki/view/Documentation/AlteraSoCDevelopmentBoard
>>>
>>
>> Are you actually using the SoCDK or some custom board ?
>>
> I've got two boards here.
> The Altera Cyclone V SoC FPGA Development Kit Board RevC
> which is the SocDK right?

Yes, that's the SoCDK.

Can you confirm to me whether or not the SoCDK boots reliably in the
default configuration provided with u-boot-socfpga/ddr branch, with DRAM
calibration always passing?

If the MMC fails, can you show me how do you test the MMC ?

I will try the SOCDK later, once I have some time. Boot/output log would
really help too.

> And our own board design.
>
> Our design works fine with new uboot's.
> Just can't get things to work with the dek kit.
> It's fairly similar to the SocDK
> 
> I'm building two different version of uboot.
> Using the two different qts generated files.
> I've setup a separate defconfig / dts and board config for our board.
> 
> I'd really like to find the quartus project that was used to generate
> the qts files committed into the uboot tree. All the ones I've used so
> far have different ddr timing and pin configs!

It's most likely generated from GHRD 15.0 or 15.1 , the result should be
the same either way.

-- 
Best regards,
Marek Vasut