From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dan Murphy Date: Thu, 7 Apr 2016 11:02:53 -0500 Subject: [U-Boot] [uboot][PATCH v3 1/2] net: phy: dp83867: Add device tree bindings and documentation In-Reply-To: <5705E5DA.1050208@ti.com> References: <1459942680-18696-1-git-send-email-dmurphy@ti.com> <5705E5DA.1050208@ti.com> Message-ID: <570684AD.1080704@ti.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Mugunthan On 04/06/2016 11:45 PM, Mugunthan V N wrote: > On Wednesday 06 April 2016 05:07 PM, Dan Murphy wrote: >> Add the device tree bindings and the accompanying documentation >> for the TI DP83867 Giga bit ethernet phy driver. >> >> The original document was from: >> [commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel] >> >> Signed-off-by: Dan Murphy >> --- >> >> v3 - Modify the binding to the kernel changed int -> internal for the delay - https://patchwork.ozlabs.org/patch/606595/ >> >> doc/device-tree-bindings/net/ti,dp83867.txt | 29 ++++++++++++++++++++++++ >> include/dt-bindings/net/ti-dp83867.h | 35 +++++++++++++++++++++++++++++ >> 2 files changed, 64 insertions(+) >> create mode 100644 doc/device-tree-bindings/net/ti,dp83867.txt >> create mode 100644 include/dt-bindings/net/ti-dp83867.h >> >> diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt >> new file mode 100644 >> index 0000000..0ec009c >> --- /dev/null >> +++ b/doc/device-tree-bindings/net/ti,dp83867.txt >> @@ -0,0 +1,29 @@ >> +* Texas Instruments - dp83867 Giga bit ethernet phy >> + >> +Required properties: >> + - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h >> + for applicable values >> + - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h >> + for applicable values >> + - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h >> + for applicable values >> + >> +Default child nodes are standard Ethernet PHY device >> +nodes as described in doc/devicetree/bindings/net/ethernet.txt >> + >> +Example: >> + >> +&mac { >> + pinctrl-0 = <&davinci_mdio_default>; >> + pinctrl-1 = <&davinci_mdio_sleep>; >> + status = "okay"; >> + >> + ti,rx_internal_delay = ; >> + ti,tx_internal_delay = ; >> + ti,fifo_depth = ; >> + >> +}; > This example should in phy node and not in mac node as per the linux > commmit mentioned above? Are you saying that the code should look like this &mac { pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy at 0 { reg = <0>; ti,rx_int_delay = ; ti,tx_int_delay = ; ti,fifo_depth = ; }; This is the way it is in the kernel. uBoot cpsw code is missing the kernel patch 9e42f7152 to be able to do this. Dan > > Regards > Mugunthan V N > >> + >> + >> +Datasheet can be found: >> +http://www.ti.com/product/DP83867IR/datasheet >> diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h >> new file mode 100644 >> index 0000000..5c592fb >> --- /dev/null >> +++ b/include/dt-bindings/net/ti-dp83867.h >> @@ -0,0 +1,35 @@ >> +/* >> + * TI DP83867 PHY drivers >> + * >> + * SPDX-License-Identifier: GPL-2.0 >> + * >> + */ >> + >> +#ifndef _DT_BINDINGS_TI_DP83867_H >> +#define _DT_BINDINGS_TI_DP83867_H >> + >> +/* PHY CTRL bits */ >> +#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 >> +#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 >> +#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 >> +#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 >> + >> +/* RGMIIDCTL internal delay for rx and tx */ >> +#define DP83867_RGMIIDCTL_250_PS 0x0 >> +#define DP83867_RGMIIDCTL_500_PS 0x1 >> +#define DP83867_RGMIIDCTL_750_PS 0x2 >> +#define DP83867_RGMIIDCTL_1_NS 0x3 >> +#define DP83867_RGMIIDCTL_1_25_NS 0x4 >> +#define DP83867_RGMIIDCTL_1_50_NS 0x5 >> +#define DP83867_RGMIIDCTL_1_75_NS 0x6 >> +#define DP83867_RGMIIDCTL_2_00_NS 0x7 >> +#define DP83867_RGMIIDCTL_2_25_NS 0x8 >> +#define DP83867_RGMIIDCTL_2_50_NS 0x9 >> +#define DP83867_RGMIIDCTL_2_75_NS 0xa >> +#define DP83867_RGMIIDCTL_3_00_NS 0xb >> +#define DP83867_RGMIIDCTL_3_25_NS 0xc >> +#define DP83867_RGMIIDCTL_3_50_NS 0xd >> +#define DP83867_RGMIIDCTL_3_75_NS 0xe >> +#define DP83867_RGMIIDCTL_4_00_NS 0xf >> + >> +#endif >> -- ------------------ Dan Murphy