From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?Q?Andreas_F=c3=a4rber?= Date: Mon, 11 Apr 2016 00:24:58 +0200 Subject: [U-Boot] [PATCH] efi_loader: Always flush in cache line size granularity In-Reply-To: <1459755138-173508-1-git-send-email-agraf@suse.de> References: <1459755138-173508-1-git-send-email-agraf@suse.de> Message-ID: <570AD2BA.609@suse.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Am 04.04.2016 um 09:32 schrieb Alexander Graf: > The cache line flush helpers only work properly when they get aligned > start and end addresses. Round our flush range to cache line size. It's > safe because we're guaranteed to flush within a single page which has the > same cache attributes. > > Reported-by: Marek Vasut > Signed-off-by: Alexander Graf > --- > lib/efi_loader/efi_runtime.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c > index 22bcd08..40acec0 100644 > --- a/lib/efi_loader/efi_runtime.c > +++ b/lib/efi_loader/efi_runtime.c > @@ -194,7 +194,8 @@ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map) > #endif > > *p = newaddr; > - flush_dcache_range((ulong)p, (ulong)&p[1]); > + flush_dcache_range((ulong)p & ~(CONFIG_SYS_CACHELINE_SIZE - 1), > + ALIGN((ulong)&p[1], CONFIG_SYS_CACHELINE_SIZE)); dragonboard410c_defconfig fails to build with this due to undefined CONFIG_SYS_CACHELINE_SIZE. Do we need to #ifdef here or is the dragonboard410c at fault for not defining it? jetson-tk1_defconfig for instance builds fine with this patch. Regards, Andreas > } > > #ifndef IS_RELA -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany GF: Felix Imend?rffer, Jane Smithard, Graham Norton HRB 21284 (AG N?rnberg)